Topic
AND gate
About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.
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TL;DR: Experimental results show that the power consumption of DTL circuits depends on unpredictable initial state of T-flip-flops, and DTL randomizes thePower consumption without using random number/mask generators while its delay time is reasonable in comparison with other logic styles.
30 citations
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23 Oct 2009TL;DR: In this paper, a physics-based gate current model based on nonequilibrium electron energy distributions obtained from the spherical harmonic expansion of the Boltz-mann equation was developed. But the model is not suitable for the case of hot electron injection.
Abstract: A physics-based gate current model has been de- veloped based on nonequilibrium electron energy distributions obtained from the spherical harmonic expansion of the Boltz- mann equation. The model accounts for band structure effects, relevant microscopic scattering mechanisms, and electron injec- tions caused by tunneling and thermionic emission processes with parallel momentum conservation and image potential barrier lowering. Obtained distribution functions and injection currents agree well with Monte Carlo simulations and experiments. I. INTRODUCTION Hot carrier injection into the gate oxide in MOSFETs is responsible for gate leakage and oxide degradation, and it has been used in the write operation in NOR flash memories. In order to model the hot carrier injection current, accurate knowledge of the nonequilibrium electron energy distribution is required. Although the Monte Carlo (MC) method would be the most rigorous tool to study hot electron transport (1), the MC method involves large statistical noise in the tail distribution that is important in the gate current calcu- lation. This paper describes a gate current model based on the Spherical Harmonic Expansion (SHE) of the Boltzmann Transport Equation (BTE) (2), (3), (4), (5) that we have implemented in the device simulator Sentaurus Device (6). The implemented SHE model accounts for the full band structure obtained from the empirical pseudopotential method (EPM) (7) and microscopic scattering mechanisms caused by acoustic and intervalley phonons, ionized impurities, and impact ionization. The implemented gate current model covers tunneling and thermionic emission components, and it takes into account parallel momentum conservation, image potential induced barrier lowering, and scattering probability within the image force potential well (1). We validate our model by com- paring obtained distribution functions and gate currents with MC simulations and experiments, and provide a gate current simulation example for a long-channel MOSFET where the hot electron injection is the dominant gate current mechanism.
30 citations
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01 Oct 1990TL;DR: To show the benefits of the common-gate architecture, a 10*10-b fully pipelined multiplier was designed in custom standard cells using commercially available place-and-route software and then in an HDGA architecture.
Abstract: The properties and performance of high-density gate arrays (HDGAs) are largely determined by the structure on which logic and memory functions are mapped. An architecture for an effective implementation of these functions is presented. All architecture in which each basic cell provides three nMOS and three pMOS transistors is given. Both nMOS and pMOS transistors share a common gate. The advantages of such an architecture can be fully exploited in memory and logic array structures like ROM, RAM, and PLA. Triple-metal BiCMOS processes are at present used to implement HDGAs. Replacing the expensive third metal layer with a TiSi/sub 2/ layer increases the silicon cost and processing time by no more than 5%. These straps are used to bridge only short distances, such as those within logic cells. They are also used for connecting transistors in parallel for increased driving capability. To show the benefits of the common-gate architecture, a 10*10-b fully pipelined multiplier was designed in custom standard cells using commercially available place-and-route software and then in an HDGA architecture. >
30 citations
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TL;DR: In this paper, a flash-based FPGA was exposed to radiation to measure variations in current, temperature, propagation-delay and duty-cycle in logic circuits, and electrical simulations were carried out to study the difference of behavior in the degradation of different logic mappings.
Abstract: We exposed a flash-based FPGA to radiation to measure variations in current, temperature, propagation-delay and duty-cycle in logic circuits. Propagation-delay degradations vary from 400% to 1100% before functional failure, according to circuit and logical mapping. Electrical simulations are carried out to study the difference of behavior in the degradation of different logic mappings.
30 citations
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TL;DR: The dominant device used in the semiconductor industry today is the silicon-based metal oxide semiconductor (MOS) transistor as mentioned in this paper, which consists of a source, drain, channel, and gate region fabricated in single-crystal silicon.
Abstract: The dominant device used in the semiconductor industry today is the silicon-based metal oxide semiconductor (MOS) transistor. The MOS transistor consists of a source, drain, channel, and gate region fabricated in single-crystal silicon (Figure 1). The source region provides a supply of mobile charge when the device is turned “on.” The source is electrically isolated from the drain by the channel region, which is oppositely charged. An insulating oxide layer between the gate and the channel region forms a capacitor. During operation, a voltage is applied to the gate. By applying the appropriate voltage, a conductive layer of charge can be attracted in the channel region at the oxide/silicon interface. This layer of charge acts as a wire that effectively connects the source and drain regions. By changing the voltage on the gate, the conducting layer of charge can be removed. Thus the transistor acts like a switch, with the gate electrode controlling the connection from the source to the drain. These individual switches can be connected to form the basic building blocks for circuit design. These building blocks are used to create the high-performance microprocessors and memory chips in today's computers.
30 citations