AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Photon-Photon Quantum Phase Gate in a Photonic Molecule with χ (2 ) Nonlinearity

Abstract: The quantum logic between single photons lies at the foundation of deterministic, scalable quantum information processing. However, practical implementation suffers from weak optical nonlinearity, and gate fidelity is intrinsically limited by phase noise and spectral mixing. The authors address these concerns by utilizing an ultrahigh-$Q$ photonic microcavity with ${\ensuremath{\chi}}^{2}$ nonlinearity. Two-photon spontaneous emission is thoroughly suppressed by shutting off the coupling channels between this artificial atom and the continuum states of a waveguide. This promising scheme for room-temperature operation is almost within reach of current experiments, and can be generalized to other systems.

Modeling and VLSI design constraints of substrate current

Abstract: Some VLSI design constraints due to substrate current will be discussed and a simple closed form expression for short channel MOS transistor substrate current is proposed. This model is based on the physical operating principle of impact ionization, as well as the electric field dependence on drain and gate voltage. By using this model, the calculated substrate current of a transistor with L eff ≃ 1.5 µm was found to be within 10% of measured values over the operating range of interest. In addition, this model also correctly predicts parasitic bipolar breakdown phenomenon as a function of gate voltage. Because of its simplicity, the model has been easily implemented into a computer-aided circuit analysis program to simulate the actual circuit with very little increase in execution time.

Radio-frequency switch having dynamic body coupling

Abstract: Radio-frequency (RF) switch circuits are disclosed including at least one first field-effect transistor (FET) disposed between first and second nodes, each of the at least one first FET having a respective body and gate. The RF switch circuit may include a coupling circuit that couples the respective body and gate of the at least one first FET, the coupling circuit configured to be switchable between a resistive-coupling mode and a body-floating mode, as well as an adjustable-resistance circuit connected to either or both of the respective gate and body of the at least one FET, the adjustable-resistance circuit including a resistor in parallel with a bypass switch.

Self-aligned deep trench DRAM array device

Abstract: An integrated circuit and a method of manufacturing an integrated circuit comprises forming an insulator over a substrate, forming a trench in the insulator and the substrate, undercutting the insulator to form a gate conductor opening between the substrate and the insulator adjacent the trench, and forming a gate oxide and gate conductor in the gate conductor opening.

Statistical Timing Yield Optimization by Gate Sizing

Abstract: In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments performed in an industrial framework on combinational International Symposium on Circuits and Systems (ISCAS'85) and Microelectronics Center of North Carolina (MCNC) benchmarks show absolute timing yield gains of 30% on the average, over deterministic timing optimization for at most 10% area penalty. It is further shown that circuits optimized using our metric have larger timing yields than the same optimized using a worst case metric, for iso-area solutions. Finally, we present an insight into statistical properties of gate delays for a commercial 0.13-mum technology library which intuitively provides one reason why statistical timing driven optimization does better than deterministic timing driven optimization