AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Realization of Minimum and Maximum Gate Function in Ta2O5-based Memristive Devices.

Abstract: Redox-based resistive switching devices (ReRAM) are considered key enablers for future non-volatile memory and logic applications. Functionally enhanced ReRAM devices could enable new hardware concepts, e.g. logic-in-memory or neuromorphic applications. In this work, we demonstrate the implementation of ReRAM-based fuzzy logic gates using Ta2O5 devices to enable analogous Minimum and Maximum operations. The realized gates consist of two anti-serially connected ReRAM cells offering two inputs and one output. The cells offer an endurance up to 106 cycles. By means of exemplary input signals, each gate functionality is verified and signal constraints are highlighted. This realization could improve the efficiency of analogous processing tasks such as sorting networks in the future.

Method for making an electronic component with self-aligned drain and gate, in damascene architecture

Abstract: The invention concerns a method for making an electronic component with self-aligned source, drain and gate, comprising the following steps: a) forming on a silicon substrate (100) a dummy gate; b) forming a source (118) and a drain (120) on either side of the dummy gate; c) self-aligned surface siliconizing of the source and drain; d) depositing at least a metal coating (130, 132), called contact coating; e) replacing the dummy gate with at least a final gate (150).

Hybrid manufacture of air gap and gate of Suspended Gate FET without using spacers producing gate separately from base structure, with air gap height based on height difference of channel and field isolators

Abstract: The method is performed without adding material which must be subsequential removed. The air gap is formed by a gate produced separately from the production of the FET base structure. A chemically sensitive surface can be optionally added to the gate which is applied to the base structure as a hybrid with an air gap height resulting from the height difference between the channel (6) and field (3) isolators. USE/ADVANTAGE - For producing SGFET with freely accessible space between gate electrode and channel isolator, e.g. for use in ion concentration analysers. High purity and low surface roughness can be achieved.

Semiconductor device and display driving device using the same

Abstract: PROBLEM TO BE SOLVED: To make a leakage current small, to perform high integration, to perform formation with less processes and to make an output level be appropriate by performing constitution by the transistors of the same conductive type. SOLUTION: The respective source and drain of P type transistors 13 and 14 are serially connected between a power source and ground, positive logic or negative logic is impressed from an input (IN) side to the gate of the P type transistor 13 and logic for which input (IN) is inverted is impressed from an inverted input (IN with upper bar) side to the gate of the P type transistor 14. Then, the source and drain of the P type transistor 12 are interposed between the inverted input (IN with upper bar) to the gate of the P type transistor 14 and a capacitor 15 whose one end is connected between the P type transistor 12 and the gate of the P type transistor 14 and other end is connected between the P type transistor 13 and connection point of the P type transistor 14 is interposed. Thus, a Low level outputted from an output terminal (OUT) is corrected so as to be a potential equivalent to a ground level.

All-Optical Binary Full Adder Using Logic Operations Based on the Nonlinear Properties of a Semiconductor Optical Amplifier

Abstract: We propose a new and potentially integrable scheme for the realization of an all-optical binary full adder employing two XOR gates, two AND gates, and one OR gate. The XOR gate is realized using a Mach-Zehnder interferometer (MZI) based on a semiconductor optical amplifier (SOA). The AND and OR gates are based on the nonlinear properties of a semiconductor optical amplifier. The proposed scheme is driven by two input data streams and a carry bit from the previous less-significant bit order position. In our proposed design, we achieve extinction ratios for Sum and Carry output signals of 10 dB and 12 dB respectively. Successful operation of the system is demonstrated at 10 Gb/s with return-to-zero modulated signals.