AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Multi-level arbitration system for decentrally allocating resource priority among individual processing units

Abstract: A decentralized arbitrator includes an individual elementary arbitrator and a level elementary arbitrator for each arbitration unit. Determination of the priority due to one unit, when no other unit claims priority, is accelerated by directing the request states of all units on the same level and on all other levels to the input of an AND gate, the output of which is connected to the bus-utilization enablement input of the relevant unit, through an OR gate and a D flip-flop.

Runtime verification of embedded real-time systems

Abstract: We present a runtime verification framework that allows on-line monitoring of past-time Metric Temporal Logic (ptMTL) specifications in a discrete time setting. We design observer algorithms for the time-bounded modalities of ptMTL, which take advantage of the highly parallel nature of hardware designs. The algorithms can be translated into efficient hardware blocks, which are designed for reconfigurability, thus, facilitate applications of the framework in both a prototyping and a post-deployment phase of embedded real-time systems. We provide formal correctness proofs for all presented observer algorithms and analyze their time and space complexity. For example, for the most general operator considered, the time-bounded Since operator, we obtain a time complexity that is doubly logarithmic both in the point in time the operator is executed and the operator's time bounds. This result is promising with respect to a self-contained, non-interfering monitoring approach that evaluates real-time specifications in parallel to the system-under-test. We implement our framework on a Field Programmable Gate Array platform and use extensive simulation and logic synthesis runs to assess the benefits of the approach in terms of resource usage and operating frequency.

An Efficient Circuit Compilation Flow for Quantum Approximate Optimization Algorithm

Abstract: Quantum approximate optimization algorithm (QAOA) is a promising quantum-classical hybrid algorithm to solve hard combinatorial optimization problems. The two-qubits gates used in quantum circuit for QAOA are commutative i.e., the order of gates can be altered without changing the logical output. This re-ordering leads to execution of more gates in parallel and a smaller number of additional gates to compile the QAOA circuit resulting in lower circuit depth and gate-count which is beneficial for circuit run-time and noise. A lower number of gates means a lower accumulation of gate errors, and a lower circuit depth means the quantum bits will have a lower time to decohere (lose state). However, finding the best re-ordered circuit is a difficult problem and does not scale well with circuit size. This paper presents a compilation flow with 3 approaches to find an optimal re-ordered circuit with reduced depth and gate count. Our approaches can reduce gate count up to 23.21% and circuit depth up to 53.65%. Our approaches are compiler agnostic, can be integrated with existing compilers, and scalable.

Integrated circuit controller programmable with unidirectional-logic instructions representative of sequential wire nodes and circuit elements of a ladder diagram

Abstract: A programmable controller that is programmed to simulate a ladder diagram and accepts input signals to control output devices in accordance with the ladder diagram program and comprising, in addition to a main memory that stores the program, a logic processor and input/output circuits, of a special wire number memory and a control coil memory for receiving, storing and making available to the processor the result of every logic function representing the current on-off status of each wire node and each control coil and associated contacts. This controller affords the maintenance of a complete current record of the changing status of the contacts and their interconnecting circuit nodes. This makes possible a particularly simple unidirectional-logic programming mode because the programmer does not have to keep track of which logic operations must be temporarily stored. This storage affords a powerful monitoring means in that signal tracing can be accomplished by merely calling up predetermined wire numbers from the special wire number memory and displaying the status thereof, or calling up predetermined input devices or control coils to view the status thereof. Moreover, for maintenance purposes, this architecture provides a selector switch and logic circuitry whereby a predetermined wire node may be manually forced "on" or "off" for maintenance purposes or the like.

A simple, precise, and low jitter delay/gate generator

Abstract: The generator of precise delay over the range of 0–650 μs is described. The delay is selected with 10 ps resolution and its jitter is below 8 ps (rms) for delays up to 10 μs. The generator was designed as a complementary metal-oxide-semiconductor programmable logic device driven by a signal generator. Three output pulses are generated: START, STOP, and GATE, all with the amplitude of 2.3 V and the switching times below 500 ps.