AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together

Abstract: This paper presents an integrated design flow which combines floorplanning, technology mapping, and placement using a dynamic programming algorithm. The proposed design flow consists of five steps: maximum tree sub-structure formation, levelized cluster tree construction, minimum area implementation using 2-D shape functions, critical path identification, and repeated application of simultaneous floorplanning, technology mapping and gate placement along the timing critical paths. Experimental results obtained from an extensive set of benchmarks demonstrate the effectiveness of the proposed flow.

On the modeling and testing of gate oxide shorts in CMOS logic gates

Abstract: The electrical and logic operation of CMOS simple logic gates in the presence of gate oxide shorts is analyzed using realistic defect models. These models reflect the resistive nature of gate oxide shorts and the difference between n- and p-channel transistors. The resistance of a short plays a central role in determining the actual circuit behavior. Faults caused by gate oxide shorts can be dependent not only on inputs to the gate containing the fault but also on other signals in the circuit, and can escape tests generated using normal TPG schemes. The stuck-at test set for a logic gate cannot guarantee to detect all transistor gate-to-source and gate-to-drain shorts in the logic gate. Gate oxide shorts in n-channel transistors affect circuit operation more severely than those in p-channel transistors do. Some limitations of present transistor-level fault modeling techniques are revealed. >

N{40 th power galois linear gate

Abstract: A configuration of two-level Boolean elements for implementing an n'th power Galois linear gate on a single medium scale integrated circuit chip is disclosed. The illustrated configuration includes orthogonally arranged sets of four parallel X input lines and four parallel Y input lines having each of their sixteen intersections intercoupled by a two-input AND gate. The outputs of the AND gates are, in turn, coupled to seven internal EXCLUSIVE OR gates and four output EXCLUSIVE OR gates. A separate Z input line is coupled to each of the four output EXCLUSIVE OR gates for providing the function G(X)G(Y) + G(Z) = G(XY + Z).

Control circuitry for electronic musical instrument

Abstract: In an electronic musical instrument of the type including a keyboard and a resistor voltage divider having points there along respectively coupled by way of actuable keys associated with the keyboard to a single output bus, there is provided improved control electronics having output signals that control, for example, an envelope generator and a voltage controlled oscillator. The control electronics includes an oscillator and gate circuit coupled to the bus for providing a gate output signal which is present as long as at least one key is actuated, a sample/hold circuit coupled to the bus for providing a control voltage signal the amplitude of which is a function of the position of the actuated key, and a trigger signal means coupled to the keyboard and responsive to the gate circuit and the actuation of two or more keys for providing a trigger signal of shorter duration than the gate signal and occurring near the commencement of the gate signal.

A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction

Abstract: Input vector control (IVC) technique is based on the observation that the leakage current in a CMOS logic gate depends on the gate input state, and a good input vector is able to minimize the leakage when the circuit is in the sleep mode. The gate replacement technique is a very effective method to further reduce the leakage current. In this paper, we propose a fast algorithm to find a low leakage input vector with simultaneous gate replacement. Results on MCNC91 benchmark circuits show that our algorithm produces $14 %$ better leakage current reduction with several orders of magnitude speedup in runtime for large circuits compared to the previous state-of-the-art algorithm. In particular, the average runtime for the ten largest combinational circuits has been dramatically reduced from 1879 seconds to 0.34 seconds.