AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Hot-electron currents in deep-submicrometer MOSFETs

Abstract: A comprehensive study of hot-electron-induced substrate and gate currents in deep-submicrometer MOSFETs is presented. The substrate- and gate-current characteristics for devices with channel lengths as small as 0.2 mu m and oxide thickness as thin as 55 AA are examined. Implications for MOSFET reliability and EPROM programming are discussed. In the deep-submicrometer regime, established hot-electron concepts and models are found to be applicable; however, consideration of the finite depth of the current path and current-crowding-induced weak gain control becomes much more important. With these modifications, physical analytical models for substrate and gate currents are developed and verified for deep-submicrometer devices. >

Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware

Abstract: In this paper an area efficient multiplier-less hardware architecture is proposed for the implementation of an integrate- and-fire SNN model. The proposed architecture is intended for large scale implementation on a single FPGA. A modular design is proposed in order to make it flexible. Synaptic multiplication is performed with a simple AND gate, and pulses from different synapses are added together at different times, replicating the accumulation of synaptic inputs for the membrane potential. In order to introduce non-linearity into the membrane potential a normalized random number is introduced to this state variable. The proposed architecture uses spike trains as an input much like those in real networks

Gate simulation and lower bounds on the simulation time

Abstract: Unitary operations are the building blocks of quantum programs. Our task is to design efficient or optimal implementations of these unitary operations by employing the intrinsic physical resources of a given $n$-qubit system. The most common versions of this task are known as Hamiltonian simulation and gate simulation, where Hamiltonian simulation can be seen as an infinitesimal version of the general task of gate simulation. We present a Lie-theoretic approach to Hamiltonian simulation and gate simulation. From this, we derive lower bounds on the time complexity in the $n$-qubit case, generalizing known results to both even and odd $n$. To achieve this we develop a generalization of the so-called magic basis for two-qubits. As a corollary, we note a connection to entanglement measures of concurrence-type.

Electrical-logic simulation and its applications

Abstract: Electrical-logic (ELogic) is a form of circuit modeling and simulation that solves for the amount of time required for a network variable to make a particular change, rather than solving for the network variables at the given time point as in conventional circuit simulation. Three ELogic algorithms are presented. The algorithms are based on the nodal analysis method and provide a continuous speed-precision tradeoff between the circuit level and logic/switch level, as well as providing more accurate timing information than existing strength-oriented logic simulation or switch-level simulation at comparable speed. These ELogic algorithms have been used to implement both a simulator, ELOSIM, and a timing verifier, E-Crystal, and experimental results from these programs are also included. >

A recursive fast multiplier

Abstract: This paper presents a recursive fast multiplication algorithm. The paper defines the algorithm and applies it to two's complement signed multiplication. A step-by-step approach is given that discusses the architectural and logic implementation in detail. A random, self-checking, simulation program verifies the correctness of the recursive multiplication algorithm. The paper analyzes the speed and gate count of the design and compares the results to other multiplier designs.