Topic
AND gate
About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.
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Patent•
31 Oct 1996TL;DR: In this article, the first and second comparison outputs are generated by bit-wise comparing first-and second portions of the bus with first/second expected signal patterns, and the logical AND of the respective comparison results may be treated as the first or second comparison output.
Abstract: Circuitry for detecting signal patterns on a multi-bit bus. First comparison circuitry monitors a first portion of the bus comparing it with a first expected signal pattern, generating a first comparison output. Second comparison circuitry monitors a second portion of the bus comparing it with a second expected signal pattern, generating a second comparison output. Both comparison outputs are applied to an AND gate and a first OR gate. One data input of a multiplexer is coupled to the output of the first OR gate. Another data input is coupled to the output of the AND gate. Another data input is coupled to the first comparison output, and another data input is coupled to the second comparison output. One input of a second OR gate may be coupled to the multiplexer output, and another input coupled to a disable indicator, allowing the multiplexer output to be overridden. The first and second comparison outputs may be generated by bit-wise comparing first and second portions of the bus with first and second expected signal patterns. The logical AND of the respective comparison results may be treated as the first and second comparison outputs, or they may be treated as first and second intermediate bits. These first and second intermediate bits may be ORed with first and second mask bits, and the results may be treated as the first and second comparison outputs. The outputs of the two OR operations may also be EXCLUSIVE ORed with first and second negate bits, respectively.
28 citations
TL;DR: It is demonstrated theoretically and experimentally that spatiotemporal solitons can be generated through noncollinear second-harmonic generation and could be used to implement an optical AND gate with ultrafast, high-contrast operation but without sensitivity to the phases of the input pulses.
Abstract: We demonstrate theoretically and experimentally that spatiotemporal solitons can be generated through noncollinear second-harmonic generation. The resulting Y geometry could be used to implement an optical AND gate with ultrafast, high-contrast operation but without sensitivity to the phases of the input pulses.
28 citations
TL;DR: The first ever implementation of a thermal AND gate, which performs logic calculations with phonons, is presented using two identical thermal diodes composed of asymmetric graphene nanoribbons (GNRs).
Abstract: The first ever implementation of a thermal AND gate, which performs logic calculations with phonons, is presented using two identical thermal diodes composed of asymmetric graphene nanoribbons (GNRs). Employing molecular dynamics simulations, the characteristics of this AND gate are investigated and compared with those for an electrical AND gate. The thermal gate mechanism originates through thermal rectification due to asymmetric phonon boundary scattering in the two diodes, which is only effective at the nanoscale and at the temperatures much below the room temperature. Due to the high phonon velocity in graphene, the gate has a fast switching time of ≈100 ps.
28 citations
Patent•
07 Jun 1995
TL;DR: In this paper, a system and method for disabling and re-enabling PCI-compliant devices in a computer system is presented, which includes a CPU, a host bus coupled to the CPU, and a PCI/Host bridge coupled with the host bus.
Abstract: A system and method for disabling and re-enabling PCI-compliant devices in a computer system is disclosed. The system includes a CPU, a host bus coupled to the CPU, a PCI/Host bridge coupled to the host bus, one or more PCI-compliant devices, a PCI bus coupling the PCI/Host bridge and the PCI-compliant devices, and a device, typically in the form of a digital gate, for selectively disabling or re-enabling one or more of the PCI-compliant devices. The disclosed method operates in connection with a computer system having a CPU, a PCI/Host bridge coupled to the CPU and capable of sending an IDSEL signal to the IDSEL input pin of a target PCI-compliant device when attempting a read or write operation on the target PCI-compliant device, and one or more system I/O registers having a CONFIG ENABLE bit that reflects a user's request to disable or re-enable a PCI-compliant device. The method intercepts the IDSEL signal before it reaches the IDSEL input pin of the target PCI-compliant device, provides the intercepted IDSEL signal to the input of a digital gate such as an AND gate, provides a signal corresponding to the CONFIG ENABLE bit to the input of the same digital gate, and delivers the resulting output signal from the digital gate to the IDSEL input pin of the target PCI-compliant device.
27 citations
Patent•
06 Jul 1999
TL;DR: In this article, a flip-flop switch is driven depending on the state of a flipflop circuit, and a comparator outputs a first reset signal when an inductor current reaches the instruction value signal.
Abstract: A switch arranged between a DC power supply source and a load is driven depending on the state of a flip-flop circuit. An error amplifier outputs an instruction value signal determined based on an output voltage. A comparator outputs a first reset signal when an inductor current reaches the instruction value signal. An oscillator generates a set pulse. A first AND gate feeds as a second reset signal an AND-operation result between the Q-output of the flip-flop circuit and the first reset signal to the reset terminal of the flip-flop circuit and the negative logic input terminal of a second AND gate. The second AND gate feeds the set pulse to the set terminal of the flip-flop circuit according to the second reset signal.
27 citations