AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High- $k$ /Metal Gate Stacks Directly on SiGe

Abstract: This letter addresses mechanisms responsible for a high gate leakage current (Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k /metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (ges3%) into high- k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ~ 0.9 nm with J g comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.

Method for manufacturing semiconductor device incorporating DRAM section and logic circuit section

Abstract: In a method for manufacturing a semiconductor device incorporating a DRAM section and a logic circuit section, a refractory metal layer is formed to cover a bit line of the DRAM section, and a gate electrode and impurity diffusion regions of the logic circuit section. Then, a heating operation is performed upon sadi refractory metal layer, so that metal silicide layers are formed in the bit line of the DRAM section, and the gate electrode and the impurity diffusion regions of the logic circuit section.

Bi-directional floating gate nonvolatile memory

Abstract: A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage. The memory transistors can be integrated into a contactless array architecture having approximately one global bit/virtual ground line for every four floating gates along a row.

Magnonic interferometric switch for multi-valued logic circuits

Abstract: We investigated a possible use of the magnonic interferometric switches in multi-valued logic circuits. The switch is a three-terminal device consisting of two spin channels where input, control, and output signals are spin waves. Signal modulation is achieved via the interference between the source and gate spin waves. We report experimental data on a micrometer scale prototype based on the Y3Fe2(FeO4)3 structure. The output characteristics are measured at different angles of the bias magnetic field. The On/Off ratio of the prototype exceeds 13 dB at room temperature. Experimental data are complemented by the theoretical analysis and the results of micro magnetic simulations showing spin wave propagation in a micrometer size magnetic junction. We also present the results of numerical modeling illustrating the operation of a nanometer-size switch consisting of just 20 spins in the source-drain channel. The utilization of spin wave interference as a switching mechanism makes it possible to build nanometer-...

Thin film transistor array

Abstract: PURPOSE:To improve considerably the yield of a TFT array by providing two TFTs per one picture element and connecting their gate electrodes to two scanning lines which are adjacent to each other with the picture element between them. CONSTITUTION:Two TFTs (T21A and T21B) are provided for one picture element (for example, C21), and their sources are connected to a common signal line Y1, and gates are connected to scanning lines (X2 and X3) which are adjacent to each other with the picture element between them, and drains are connected to the picture element electrode of the picture element C21. If short-circuit occurs between the gate and the source of the TFT T21B because of a process defect, a line defect is generated to make an evil case. At this time, the gate of the TFT T21B is disconnected from the scanning line X3. The method where a laser beam is irradiated to the gate part to evaporate a metal of the gate connecting part, or the like is used as the disconnecting means, and the gate of each TFT is so formed that it is easily cut in a connection part 28 to the scanning line.