AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Transistor with an offset gate structure

Abstract: At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused layers. A gate electrode is formed on the gate insulating film. Sidewalls are formed on the sides of the gate insulating film and gate electrode, extending upward from the substrate. In this invention, the sidewalls are composed of material whose permittivity is higher than that of the gate insulating film, for example, of a silicon nitride film.

Semiconductor storage device

Abstract: PURPOSE:To easily detect an address of a cell from the external by providing an output circuit which uses one external terminal other than the address terminal to output the detection signal of a detecting circuit to the external and a mode switching circuit which validates the output circuit only when a test signal is applied to another external terminal. CONSTITUTION:At the test time, a voltage higher than that for normal operation is applied to a terminal 6 to set the output of a mode switching circuit 3 using a high voltage detecting buffer BUF0 to the high level. Though the output of a buffer BUF1 of the normal operation mode is set to the high level also, an output the inverse of CE of an AND gate AND10 goes to the low level because the output of an inverter INV1 goes to the low level. Simultaneously, an output the inverse of OE of an AND gate AND11 goes to the low level, and therefore, the memory is set to the read mode. In case of S=1 (presence of error), the output of an inverter INV3 goes to the low level and is outputted to the external through a terminal 7 to indicate the presence of error; but in case of S=0 (absence of error), the output of an inverter INV2 goes to the high level. Thus, the address of an error bit is easily detected from the external.

Non-volatile memory cell and logic transistor integration

Abstract: A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region A first dielectric layer is formed over the control gate A sacrificial layer is formed over the first dielectric layer and planarized A patterned masking layer is formed over the sacrificial layer which includes a first portion which defines a select gate location laterally adjacent the control gate in the NVM region and a second portion which defines a logic gate in a logic region Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location A second dielectric layer is formed over the first portion and planarized to expose the first portion The first portion is removed to result in an opening at the select gate location A gate dielectric layer and a select gate are formed in the opening

Programmable logic device placement method utilizing weighting function to facilitate pin locking

Abstract: A method for placing a logic function into the function blocks of a complex programmable logic device (CPLD) to maintain the same input/output pin locations after the logic function is subsequently modified by a user. The method utilizes a weighting function to assign portions of the logic function to the function blocks such that sufficient resources are available in each function block to implement subsequent modifications to the logic function without changing the originally-assigned input and output pin locations. For each portion of the logic function, the weighting function is employed to identify the function block which implements the portion while maximizing the available resources in all of the function blocks. If a particular equation cannot be placed, the method utilizes a corrective measure such as fitting refinement, buffering and logic reformulation to place the equation. If the equation still cannot be placed, the weighting function is altered, thereby changing the criteria by which logic portions are assigned to the function blocks. The placement method is then repeated with the altered weighting function.

Simultaneous multichannel wavelength multicasting and XOR logic gate multicasting for three DPSK signals based on four-wave mixing in quantum-dot semiconductor optical amplifier

Abstract: In this paper, we experimentally demonstrate simultaneous multichannel wavelength multicasting (MWM) and exclusive-OR logic gate multicasting (XOR-LGM) for three 10Gbps non-return-to-zero differential phase-shift-keying (NRZ-DPSK) signals in quantum-dot semiconductor optical amplifier (QD-SOA) by exploiting the four-wave mixing (FWM) process. No additional pump is needed in the scheme. Through the interaction of the input three 10Gbps DPSK signal lights in QD-SOA, each channel is successfully multicasted to three wavelengths (1-to-3 for each), totally 3-to-9 MWM, and at the same time, three-output XOR–LGM is obtained at three different wavelengths. All the new generated channels are with a power penalty less than 1.2dB at a BER of 10−9. Degenerate and non-degenerate FWM components are fully used in the experiment for data and logic multicasting.