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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


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Patent
13 Mar 2000
TL;DR: In this paper, a method for secure multiparty computation is described in which participants agree upon a function to be computed and a representation of the function as a circuit with at least one gate Logical tables are then generated for each gate.
Abstract: A method for secure multiparty computation is disclosed In one embodiment, participants to a secure computation agree upon a function to be computed and a representation of the function as a circuit with at least one gate Logical tables are then generated for each gate A logical table includes all possible input and output values for the gate based on the function These input and output values are then encoded and the encoded tables are passed through a mix network, which generates a blinded table for each encoded logical table A blinded table corresponds to the encoded logical table except that its rows are randomly permuted and entries are encrypted After this initial blinding round, participants provide encryptions of their encoded secret inputs The participants then jointly compute the function of interest using the encrypted secret inputs and the representative circuit To simulate a gate therein, the participants compare the encrypted inputs to the gate with each encrypted input entry in the blinded table until a match is detected When a match is detected, the corresponding output entry in the matched row is taken to be the output of the gate This method of mixing and matching is performed in an identical manner for every gate in the circuit, irrespective of the layer in which it resides or the function being computed, until the output of the last gate is identified

27 citations

Journal ArticleDOI
TL;DR: In this article, a unique attempt to identify the zero-temperature-coefficient (ZTC ) point and other performance metrics for single gate, double gate, and gate stack double gate (GS-DG), ultra-thin body (UTB) silicon on insulator (SOI) n-MOSFET over a wide range of temperatures (100-400 K) through 2-D device simulation was made.

27 citations

Journal ArticleDOI
Yawei Lv1, Qijun Huang1, Hao Wang1, Sheng Chang1, Jin He1 
TL;DR: In this paper, a tunnel FET (TFET) combining both graphene nanoribbon (GNR) heterojunction (HJ) and gate work function (WF) engineering is studied with the numerical simulation.
Abstract: In this letter, a tunnel FET (TFET) combining both graphene nanoribbon (GNR) heterojunction (HJ) and gate work function (WF) engineering is studied with the numerical simulation. The lowest subthreshold swing is smaller than 15 mV/decade and the ON state current ( $I_{{\mathrm{\scriptscriptstyle ON}}}$ ) reaches to $1.7~\mu \text{A}$ with device width smaller than 3 nm. The tunnel width is well reduced with the dual-material gate (DMG) structure boosting the ON current. The channel with a wide energy gap ( $E_{g}$ ) GNR can effectively reduce the leakage current at OFF state when its length is 13 nm. It is found out that large WF difference between the gate and the GNR not only effectively enhances the tunneling effect but also leads to an electron quantum well hindering the regulation capability of the gate. This effect can be well reduced with large WF gate material on the top of the HJ region. The numerical simulation reveals that the GNR HJ-DMG TFET is a good candidate for low power applications.

27 citations

Patent
Jeon Yoo Nam1
10 Sep 2009
TL;DR: In this article, the gap-fill characteristic of contact plugs coupled to junctions can be improved and degradation in the data retention characteristic can also be prevented by using a pre-metal dielectric layer.
Abstract: A method of fabricating a semiconductor device, in which although a metal layer is included in a gate pattern, the gap-fill characteristic of contact plugs coupled to junctions can be improved and degradation in the data retention characteristic can also be prevented. According to the method, a semiconductor substrate in which lower gate patterns and gate hard mask patterns are sequentially stacked is first provided. Junctions are formed in the semiconductor substrate on both sides of each of the lower gate patterns. A first pre-metal dielectric layer is formed over the semiconductor substrate in which the hard mask patterns and the junctions are formed. Contact holes through which the junctions are exposed are formed in the first pre-metal dielectric layer. Gate trenches through which the lower gate patterns are exposed are formed by removing the hard mask patterns. Upper gate patterns, each including a metal layer, are formed in the gate trenches, and first contact plugs are formed in the contact holes.

27 citations

Journal ArticleDOI
TL;DR: This paper presents a low-cost HT gate driver developed with discrete transistors and signal diodes rated at 180–200 , which has a robust overcurrent and undervoltage lock out protection circuit.
Abstract: SiC MOSFET can operate at a junction temperature of 200–250 $^{\circ }$ C due to its improved material properties and thermal stability. However, successful realization of SiC MOSFET based high-temperature (HT) converter requires HT gate drivers. This paper presents a low-cost HT gate driver developed with discrete transistors and signal diodes rated at 180–200 $^{\circ }$ C. The gate driver has a robust overcurrent and undervoltage lock out protection circuit. The propagation delay of the protection circuit and gate driving circuit is greatly reduced compared to commercial HT gate drivers. A comparative analysis of the developed HT gate driver using discrete components and the commercially available silicon-on-insulator technology based HT gate driver is presented. The performance of the HT gate driver is evaluated for both hard switched fault and fault under load condition at an ambient temperature of 180 $^{\circ }$ C.

27 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372