AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Numerical analysis of Double Gate and Gate All Around MOSFETs with bulk trap states

Abstract: This paper investigates the scaling capability of Double Gate (DG) and Gate All Around (GAA) MOSFETs using a numerical analysis of the two-dimensional coupled Boltzmann distribution-Poisson equations in which the traps effects have been considered. Using this numerical model, we have studied the effects of the defects on the scalability limits of DG and GAA MOSFETs and compared their performances. We have found that, the scaling capability of both architectures made in recrystallized silicon will be improved as the diameter (or silicon thickness for DG structure) of device is reduced, because the small device size decreases the defect density in the channel.

Machine learning method for state preparation and gate synthesis on photonic quantum computers

Abstract: We show how techniques from machine learning and optimization can be used to find circuits of photonic quantum computers that perform a desired transformation between input and output states. In the simplest case of a single input state, our method discovers circuits for preparing a desired quantum state. In the more general case of several input and output relations, our method obtains circuits that reproduce the action of a target unitary transformation. We use a continuous-variable quantum neural network as the circuit architecture. The network is composed of several layers of optical gates with variable parameters that are optimized by applying automatic differentiation using the TensorFlow backend of the Strawberry Fields photonic quantum computer simulator. We demonstrate the power and versatility of our methods by learning how to use short-depth circuits to synthesize single photons, Gottesman-Kitaev-Preskill states, NOON states, cubic phase gates, random unitaries, cross-Kerr interactions, as well as several other states and gates. We routinely obtain high fidelities above 99\% using short-depth circuits, typically consisting of a few hundred gates. The circuits are obtained automatically by simply specifying the target state or gate and running the optimization algorithm.

Semiconductor device and manufacturing method thereof for reducing the area of the memory cell region

Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3 a between a gate 2 a and gate 2 b and connects an active region 1 a and an active region 1 b. This eliminates the necessity for providing a contact between the gate 2 a and the gate 2 b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2 c is retreated from the gate 2 a and a local wiring 3 b which connects the active region 1 b and gate 2 c disposed in a diagonal direction is adopted. This allows the gate 2 a to be shifted toward the center of the memory cell region C.

Time-Dependent Variability Related to BTI Effects in MOSFETs: Impact on CMOS Differential Amplifiers

Abstract: With the continuous transistor scaling, device mismatch related to intrinsic process variability increases and becomes one of the most important problems to be faced during circuit design. In addition, gate oxide wear-out strongly affects the device reliability and adds a time dependence to device mismatch. In this paper, the impact on circuit functionality of both process variability and gate oxide degradation is studied. First, the effect of the gate oxide damage on the NMOS and PMOS transistor characteristics and their variability has been analyzed. Second, a methodology based on combined SPICE and Monte Carlo simulations to analyze the time-dependent variability at device and circuit levels is presented, which has allowed to reproduce the experimental data. Finally, using the proposed methodology, the influence of the process variability and gate oxide wear-out on the functionality of different configurations of an amplifier circuit was investigated. The results show that both aspects can be decisive in the circuit reliability.

Linearity and Analog Performance Analysis of Double Gate Tunnel FET: Effect of Temperature and Gate Stack

Abstract: 1 Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi, India rakhinarang@gmail.com, mridula@south.du.ac.in 2 Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India saxena_manoj77@yahoo.co.in 3 Department of Electronics and Communication Engineering, Maharaja Agrasen Institute Of Technology, Sector-22, Rohini, Delhi, India rsgu@bol.net.in