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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


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Journal ArticleDOI
TL;DR: In this article, a computer model has been developed that simulates charge transport of carriers in a surface channel charge-coupled device, based on the charge continuity and current transport equations with a time dependent surface field.
Abstract: A computer model has been developed that simulates charge transport of carriers in a surface channel charge-coupled device This model is based on the charge continuity and current transport equations with a time dependent surface field The device structure of the model includes a source diffusion an input gate and transfer gate The present model is the first real simulation of the input scheme of the surface-channel CCDs The scooping and spilling techniques associated with the charge injection process are simulated by the input diffusion which is included in the model As an application to a CCD practical problem the present model has been used to study the linearity of the electrical charge injection into surface channel charge-coupled devices The generated harmonic components of a sinusoidal input are calculated using the transfer characteristics of the input stage obtained from the computer simulation Using this model the spatial variations of the self-induced fringing field and total currents under the storage and transfer gates were computed The charge transfer mechanisms for short-gate ( L ≤ 8 μ m) CCDs was investigated It was found that for short gates the charge transfer efficiency is governed mainly by the fringing field and self-induced current mechanisms The results of this study help to clarify the mechanism by which the signal-charge level and gate length affect the charge transfer efficiency

26 citations

Proceedings ArticleDOI
Oskar Mencer1
22 Sep 2002
TL;DR: The module generation library PAM-Blox II, the second generation of object-oriented module generators in C++, targeted at computing with FPGAs, and examples of design tradeoffs and performance results using redundant representations for addition and multiplication, and technology mapping of comparison and elementary function evaluation are described.
Abstract: This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmability of FPGAs, or in other words, the productivity of the FPGA programmer. We describe (1) the module generation library PAM-Blox II, the second generation of object-oriented module generators in C++, targeted at computing with FPGAs, and (2) examples of design tradeoffs and performance results using redundant representations for addition and multiplication, and technology mapping of comparison and elementary function evaluation. PAM-Blox II is built on top of a set of extensions to the gate level FPGA design library PamDC to provide a more efficient, portable, scalable, and maintainable module generator library. Using PAM-Blox II we demonstrate a simplified interface to bit-level programability. The simplification results from the bottom-up approach and a close coupling of architecture generation, module generation and gate level CAD. The tradeoffs for the module generators are based on trading area for speed and hand-optimizing technology mapping to the specific FPGA technology. As an example, we show that redundant number representations hold one key to unleashing the full potential of reconfigurability on the bit-level. The presented module generators are applied to encryption and compression to show the impact of the bit-level optimizations on application performance.

26 citations

Journal ArticleDOI
TL;DR: In this paper, the authors propose a simple and general framework for verification of quantum unitary transformations that can be applied to both individual quantum gates and gate sets, including quantum circuits.
Abstract: Efficient verification of the functioning of quantum devices is a key to the development of quantum technologies, but is a daunting task as the system size increases. Here we propose a simple and general framework for verifying unitary transformations that can be applied to both individual quantum gates and gate sets, including quantum circuits. This framework enables efficient verification of many important unitary transformations, including but not limited to all bipartite unitaries, Clifford unitaries, generalized controlled-$Z$ gates, generalized controlled-not gates, the controlled-swap gate, and permutation transformations. For all these unitaries, the sample complexity increases at most linearly with the system size and is often independent of the system size. Moreover, little overhead is incurred even if one can only prepare Pauli eigenstates and perform local measurements. Our approach is applicable in many scenarios in which randomized benchmarking (RB) does not apply and is thus instrumental to quantum computation and many other applications in quantum information processing.

26 citations

Patent
Bruce A. Richardson1
18 Nov 1986
TL;DR: In this article, a direct coupled FET logic (DCFL) circuit element has an active FET with source connected to a low reference voltage and drain connected through a pull-up FET to a higher reference voltage.
Abstract: A direct coupled FET logic (DCFL) circuit element has an active FET with source connected to a low reference voltage and drain connected through a pull-up FET to a higher reference voltage. An input is applied to the gate of the active FET and the output is taken from its drain, the pull-up FET having its gate connected to its source. In depletion mode configuration, a photodiode is connected to the gate of the active FET, the photodiode energizable to downwardly shift the gate voltage. In enhancement mode configuration, a photodiode is connected between source and gate of the pull-up transistor and is energized to shift the gate voltage upwardly. The photodiodes are integrated with the active and pull-up FETs and are energized by light or decay radiation.

26 citations

Journal ArticleDOI
TL;DR: In this article, a reconfigurable all-optical fulladder and full-subtractor based on the theee-input XOR gate and logic minterms are experimentally demonstrated using four-wave mixing (FWM) and cross-gain modulation (XGM) in four parallel semiconductor optical amplifiers.
Abstract: 40 Gbit/s reconfigurable all-optical full-adder and full-subtractor based on the theee-input XOR gate and logic minterms are experimentally demonstrated using four-wave mixing (FWM) and cross-gain modulation (XGM) in four parallel semiconductor optical amplifiers. This work is one of the first to compactly combine the capabilities of a full-adder and a full-subtractor into a single unit. Correct and clear temporal waveforms are observed. The output extinction ratio (ER) for the FWM operation is over 8 dB, and the ERs for the XGM operations are over 11 dB.

26 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372