AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Liquid crystal display device and method of driving liquid crystal display device

Abstract: The liquid crystal display device includes a liquid crystal display panel provided with source signal lines and gate signal lines arranged in matrix form and liquid crystal display elements using OCB mode liquid crystal provided at intersections between the source signal lines and gate signal lines, a gate driver which supplies a gate signal to the gate signal lines and a source driver which supplies a voltage corresponding to gradation of the display data to the source signal lines during a display period and supplies a voltage to prevent counter-transfer to the source signal lines during a counter-transfer prevention drive period, and the source driver supplies a voltage lower by a predetermined value than the voltage corresponding to the black color as the voltage to prevent counter-transfer.

A parallel processing chip with embedded DRAM macros

Abstract: A combined DRAM and logic chip has been developed for massively parallel processing (MPP) applications. A trench cell 4-Mb CMOS DRAM technology is used to fabricate the chip with an additional third-level metal layer. The 5-V 0.8-/spl mu/m technology merges 100-K gate custom logic circuits and 4.5-Mb DRAM onto a 14.7/spl times/14.7 mm/sup 2/ die. The DRAM design is based on a 32-K/spl times/9-b (288-Kb) self-consistent macro form. It has independent address inputs, data I/O ports, access control circuits, and redundancy fuses and elements. The logic part of the chip consists of eight 16-b CPUs and some broadcast logic circuits. Each CPU and two DRAM macros (64-KB) comprise a processing element (PE), and hypercube connections among eight PE's are made for the scalable MPP capability. Each chip delivers 50-MIPS of performance at 2.7 W.

Method for designing a semiconductor integrated circuit

Abstract: A semiconductor integrated circuit capabling of reducing a chip area by facilitating optimization of a chip layout and a method for designing the same has been provided. For given gate level connection description, use cell information designating gates which should be designed by employing the cell patterns prepared in advance is generated. When the gate level connection description is developed into the transistor level, hybrid connection description including mixedly transistor level and gate level is then generated by employing the cell patterns relative to the gates which being designated by the use cell information and by developing gates which being not designated by the use cell information into transistor level. A layout is then designed based on the hybrid connection description including mixedly the transistor level and the gate level.

Logic circuit arrangements using insulated-gate field effect transistors

Abstract: A clock pulse-controlled logic circuit arrangement wherein the source-drain path of a first transistor having its gate electrode supplied with a clock pulse and the source-drain paths of at least two second transistors jointly constituting a logic gate by having the respective gate electrodes supplied with data input are connected in series between a first and a second operating voltage supply point. To the junction of the first transistor and logic gate or an output point is connected an operation stabilizing circuit for replenishing the output point with a voltage signal having the same polarity as the output voltage signal to prevent any change in the level of the output voltage signal while the first transistor is rendered nonconducting.

Behavioral network graph: unifying the domains of high-level and logic synthesis

Abstract: High-level synthesis operates on internal models known as control/data flow graphs (CDFG) and produces a register-transfer-level (RTL) model of the hardware implementation for a given schedule. For high-level synthesis to be efficient it has to estimate the effect that a given algorithmic decision (e.g., scheduling, allocation) will have on the final hardware implementation (after logic synthesis). Currently, this effect cannot be measured accurately because the CDFGs are very distinct from the RTL/gate-level models used by logic synthesis, precluding interaction between high-level and logic synthesis. This paper presents a solution to this problem consisting of a novel internal model for synthesis which spans the domains of high-level and logic synthesis. This model is an RTL/gate-level network capable of representing all possible schedules that a given behavior may assume. This representation allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.