AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Field effect transistor having multiple gate electrodes surrounding the channel region

Abstract: A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

All-optical wavelength coded logic gates

Abstract: All-optical logic gates in which binary words are encoded using wavelength. A method and apparatus for processing information in this wavelength encoded format is provided. The processing may occur entirely in the optical domain. This approach is modular and enables construction of logic gates using custom wave guide chips that can be mass-produced in a manner similar to that of conventional electronic digital chips. Specific gates, such as AND, OR, EXOR, or NAND, may be "programmed" into a given chip during its fabrication to encode the desired truth table. The output states of the chip are determined by ultrafast mixing of binary encoded wavelengths in a semiconductor optical amplifier. The result is a new wavelength having a relationship to the input wavelengths determined entirely by the desired truth table. The possible clock-rates for these gates can be exceedingly high, such as several hundred Gigabits/second. The product of integer word length "N" and gate clock speed can exceed several Terabits/second and may be as high as the overall optical bandwidth of the system. Complicated multi-input functions may be constructed using this approach and dynamically programmable functions may be built in which either electrical or optical signals reconfigure a set of gates by reprogramming the inverter operations in the chips.

Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits

Abstract: A multiple-phase clock signal generator includes a phase-locked loop (PLL) for generating an oscillating signal having a predetermined frequency, a counter driven by the oscillating signal and having a plurality of outputs, and a plurality of combinational logic gates each having a plurality of inputs and an output. Selected ones of the inputs of each combinational logic gate are coupled to selected outputs of the counter to produce, at the output of each combinational logic gate, a clock signal having a particular phase. Different combinations of the outputs of the counter can be used to generate different phases.

High Resolution Application Specific Fault Diagnosis of FPGAs

Abstract: High resolution diagnosis plays a critical role in silicon debug and yield improvement. Application-dependent diagnosis is also a key component in online testing and adaptive computing. In this paper, a new technique for high resolution localization of faults in the interconnects and logic blocks of an arbitrary design implemented on a field-programmable gate array (FPGA) is presented. This work is complementary to application-independent detection methods for FPGAs. This technique can uniquely identify any single bridging, open, or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The number of test configurations for interconnect diagnosis is logarithmic to the size of the mapped design, whereas logic diagnosis is performed in only one test configuration with less than 5% overhead of built-in self diagnosis. These techniques have been further extended for multiple fault diagnosis.