AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Shift register unit and gate drive device for liquid crystal display

Abstract: A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to the source of the fifth thin film transistor, a source thereof is connected to a low voltage signal input terminal, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor. The shift register unit and the gate drive device for liquid crystal display provided in the present invention, could enable the thin film transistor used to suppress the noise in the shift register unit to maintain turning on, therefore it guarantees the reliability of the shift register unit.

Semiconductor device and semiconductor integrated circuit using the same

Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

Symmetric multilevel inverter with reduced components based on non-insulated dc voltage sources

Abstract: Multilevel inverters have an important portion in power processing in power systems. These inverters have some inherent advantages such as ability to operate with high power and voltage, improved output waveform quality and flexibility which make them attractive and more popular. This study proposes a new topology based on the non-insulated dc voltage sources for multilevel inverter with reduced number of switching devices. As a result, it reduces control complexity and gate driver circuits. The proposed topology is a general topology which can be easily extended to a desired number of voltage levels. All of the desired output voltage levels (both odd and even) can be achieved using the proposed topology. The validity of the proposed multilevel inverter is verified with both computer simulation and experimental results from a 15-level laboratory prototype.

Programmable logic array with added array of gates and added output routing flexibility

Abstract: A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1 through 102-66). The output signals from the first set of AND gates are programmably elec­trically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are program­mably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coup­led to each of the output signals from the second OR logic array and the output pins (O₁ through O₁₀) of the PLA. Because of this, different output terms can be routed to different output pins thus permitting the designer to select his pin out independently of the availability of gate within specific parts of the array.

Neural Logic Machines

Abstract: We propose the Neural Logic Machine (NLM), a neural-symbolic architecture for both inductive learning and logic reasoning. NLMs exploit the power of both neural networks---as function approximators, and logic programming---as a symbolic processor for objects with properties, relations, logic connectives, and quantifiers. After being trained on small-scale tasks (such as sorting short arrays), NLMs can recover lifted rules, and generalize to large-scale tasks (such as sorting longer arrays). In our experiments, NLMs achieve perfect generalization in a number of tasks, from relational reasoning tasks on the family tree and general graphs, to decision making tasks including sorting arrays, finding shortest paths, and playing the blocks world. Most of these tasks are hard to accomplish for neural networks or inductive logic programming alone.