AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation

Abstract: Reliability is fast becoming a major concern due to the nanometric scaling of CMOS technology. Accurate analytical approaches for the reliability evaluation of logic circuits, however, have a computational complexity that generally increases exponentially with circuit size. This makes intractable the reliability analysis of large circuits. This paper initially presents novel computational models based on stochastic computation; using these stochastic computational models (SCMs), a simulation-based analytical approach is then proposed for the reliability evaluation of logic circuits. In this approach, signal probabilities are encoded in the statistics of random binary bit streams and non-Bernoulli sequences of random permutations of binary bits are used for initial input and gate error probabilities. By leveraging the bit-wise dependencies of random binary streams, the proposed approach takes into account signal correlations and evaluates the joint reliability of multiple outputs. Therefore, it accurately determines the reliability of a circuit; its precision is only limited by the random fluctuations inherent in the stochastic sequences. Based on both simulation and analysis, the SCM approach takes advantages of ease in implementation and accuracy in evaluation. The use of non-Bernoulli sequences as initial inputs further increases the evaluation efficiency and accuracy compared to the conventional use of Bernoulli sequences, so the proposed stochastic approach is scalable for analyzing large circuits. It can further account for various fault models as well as calculating the soft error rate (SER). These results are supported by extensive simulations and detailed comparison with existing approaches.

Variational Quantum State Diagonalization

Abstract: Variational hybrid quantum-classical algorithms are promising candidates for near-term implementation on quantum computers. In these algorithms, a quantum computer evaluates the cost of a gate sequence (with speedup over classical cost evaluation), and a classical computer uses this information to adjust the parameters of the gate sequence. Here we present such an algorithm for quantum state diagonalization. State diagonalization has applications in condensed matter physics (e.g., entanglement spectroscopy) as well as in machine learning (e.g., principal component analysis). For a quantum state ρ and gate sequence U, our cost function quantifies how far $$U\rho U^\dagger$$ is from being diagonal. We introduce short-depth quantum circuits to quantify our cost. Minimizing this cost returns a gate sequence that approximately diagonalizes ρ. One can then read out approximations of the largest eigenvalues, and the associated eigenvectors, of ρ. As a proof-of-principle, we implement our algorithm on Rigetti’s quantum computer to diagonalize one-qubit states and on a simulator to find the entanglement spectrum of the Heisenberg model ground state.

Display device and driving method thereof

Abstract: A disclosed display device includes a display panel with data lines and gate lines, the gate lines including odd-numbered gate lines and even-numbered gate lines The display device also includes a timing controller to generate a gate output enable signal, and a gate output enable signal division circuit to extract odd-numbered high logic periods of the gate output enable signal to output a first gate output enable signal and to extract even-numbered high logic periods of the gate output enable signal to output a second gate output enable signal The display device further includes a gate driver to supply a first gate pulse to an odd-numbered gate line in response to the first gate output enable signal and a second gate pulse to an even-numbered gate line in response to the second output enable signal

A Current Source Gate Driver Achieving Switching Loss Savings and Gate Energy Recovery at 1-MHz

Abstract: In this paper, a new current source gate drive circuit is proposed for power MOSFETs. The proposed circuit achieves quick turn on and turn off transition times to reduce switching loss and conduction loss in power MOSFETs. In addition, it can recover a portion of the CV gate energy normally dissipated in a conventional driver. The circuit consists of four controlled switches and a small inductor (typically 100 nH or less). The current through the inductor is discontinuous in order to minimize circulating current conduction loss. This also allows the driver to operate effectively over a wide range of duty cycles with constant peak current-a significant advantage for many applications since turn on and turn off times do not vary with the operating point. Experimental results are presented for the proposed driver operating in a boost converter at 1 MHz, 5 V input, 10 V/5 A output. At 5 V gate drive, a 2.9% efficiency improvement is achieved representing a loss savings of 24.8% in comparison to a conventional driver.