AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Twin monos cell fabrication method and array organization

Abstract: Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit. The invention consists of two fabrication methods, i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication. ii) Bit line crosses word gate and control gate. The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel. Two embodiments of the present invention are disclosed.

Performance of a spin-based insulated gate field effect transistor

Abstract: Fundamental physical properties limiting the performance of spin field effect transistors are compared to those of ordinary (charge-based) field effect transistors. Instead of raising and lowering a barrier to current flow these spin transistors use static spin-selective barriers and gate control of spin relaxation. The different origins of transistor action lead to distinct size dependences of the power dissipation in these transistors and permit sufficiently small spin-based transistors to surpass the performance of charge-based transistors at room temperature or above. This includes lower threshold voltages, smaller gate capacitances, reduced gate switching energies, and smaller source-drain leakage currents.

Semiconductor device and method of manufacturing the same

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure capable of sufficiently increasing gate breakdown voltage, even in the semiconductor device in which a number of transistor cells having a trench structure are formed in a matrix shape, and gate wiring composed of a metal film is in contact with the gate electrodes of the transistors.SOLUTION: A semiconductor device comprises a cell region 10 in which transistor cells are arranged in a matrix shape. Each transistor cell has a trench structure in which recessed grooves 11 are formed in a semiconductor layer 1, a gate insulating film 4 is formed in the recessed grooves 11, and gate electrodes 5 composed of, for example, polysilicon are provided in the narrow groves 11. In order to contact a gate wiring 9 composed of a metal film, a gate pad 5a, which is successively provided with the gate electrodes 5, is formed in a recessed part 12 simultaneously provided with the recessed grooves 11.

Thin film transistor with three dimensional multichannel structure

Abstract: A thin film transistor gate structure with a three-dimensional multichannel structure is disclosed. The thin film transistor gate structure according to the present invention comprises source/drain electrodes formed so as to be spaced from and opposite to each other on a substrate; semiconductive layers, comprised of a plurality of sub-semiconductive layers, each formed in a row, each end of the sub-semiconductive layers being in ohmic-contact with the source/drain electrodes; gate insulating layers surrounding each of the semiconductive layers; and gate electrodes surrounding each of the gate insulating layers. Accordingly, the whole outerlayers of each sub-semiconductive layer surrounded by the gate electrodes serve as channel regions. As a result, the effective channel area increases, thereby improving the channel conductance and current driving ability.

Buffer insertion with accurate gate and interconnect delay computation

Abstract: Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these methods use simplified interconnect and gate delay models. These models may lead to inferior solutions since the optimized objective is only an approximation for the actual delay. We propose to integrate accurate wire and gate delay models into Van Ginneken's buffer insertion algorithm (1990) via the propagation of moments and driving point admittances up the routing tree. We have verified the effectiveness of our approach on an industry design.