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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


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Journal ArticleDOI
TL;DR: The authors propose and analyze the optical signal processing functionality of periodic structures consisting of alternating layers of materials possessing different Kerr nonlinearities and propose a family of optical limiters whose output signal clamps to a set upper logic level for any input value exceeding a chosen threshold.
Abstract: The authors propose and analyze the optical signal processing functionality of periodic structures consisting of alternating layers of materials possessing different Kerr nonlinearities. They explore structure-materials-performance relationships in all-optical analog-to-digital converters, hardlimiters, and AND and OR gates. They show that their proposed analog-to-digital converters can extract a binary word from multilevel optical signals in a single bit interval. They also propose a family of optical limiters whose output signal clamps to a set upper logic level for any input value exceeding a chosen threshold. They explore the performance of an all-optical logic gate whose forward-directed output implements a binary AND and whose backward-directed output implements an OR function.

114 citations

Proceedings ArticleDOI
01 Dec 2009
TL;DR: In this article, a zero interface layer and optimized gate-electrode are used to achieve ultra low EOT and Tinv values of ∼5 A and ∼8 A respectively for both n and pMOS devices.
Abstract: A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO 2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ∼5 A and ∼8 A respectively for both n and pMOS devices. The drive currents at I off =100 nA/µm with V DD =1 V is 1.4 mA/µm and 0.6 mA/µm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V T of 0.3/-0.4V, good V T -uniformity, and V T -matching and very high cutoff frequencies at ∼290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.

113 citations

Proceedings ArticleDOI
09 Nov 2003
TL;DR: A probabilistic-based design methodology for designing nanoscale computer architectures based on Markov Random Fields (MRF), which can express arbitrary logic circuits and logic operation by maximizing the probability of state configurations in the logic network.
Abstract: As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this paper, we propose a probabilistic-based design methodology for designing nanoscale computer architectures based on Markov Random Fields (MRF). The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures based on the belief propagation algorithm. Belief propagation is a way of organizing the global computation of marginal belief in terms of smaller local computations. We will illustrate the proposed design methodology with some elementary logic examples.

113 citations

Patent
03 Feb 2014
TL;DR: In this paper, the first and second gate conductive layers of a semiconductor memory device are stacked on top of each other, and the second gate conductsance is extended to continuously cover surfaces of the first gate conductance.
Abstract: Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

113 citations

Journal ArticleDOI
TL;DR: In this paper, thin-body tunneling field effect transistors (TFETs) built on SOI substrates with both SiO 2 and HfO 2 gate dielectrics are investigated.
Abstract: We report on thin-body tunneling field-effect transistors (TFETs) built on SOI substrates with both SiO 2 and HfO 2 gate dielectrics. The source–drain leakage current is suppressed by the introduction of an intrinsic region adjacent to the drain, reducing the electric field at the tunnel junction in the off state. We also investigate the temperature dependence of the TFET characteristics and demonstrate that the temperature-induced change in the Si bandgap is the main mechanism that determines the tunneling barrier and hence the drain current I D . We present a model of the TFET as a combination of a gated diode and a MOSFET, which can be solved analytically and can predict the experimentally measured I D over a wide range of drain and gate bias. Finally we report on the low frequency noise (LFN) behavior of TFETs, which unlike conventional MOSFETs exhibits 1/ f 2 frequency dependence even for large gate areas. This dependence indicates less trapping due to the much smaller effective gate length over the tunneling junction.

112 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372