AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Method of forming mosfet

Abstract: A method for fabricating a metal oxide silicon field effect transistor (MOSFET) wherein a polysilicon layer is deposited over a gate oxide film serving to insulate the gate of the MOSFET from the substrate of the MOSFET The polysilicon layer serves to prevent the gate oxide film from being etched upon forming a gate electrode using a metal film or metal silicide side walls as a mask Accordingly, it is possible to prevent a short circuit from occurring between the semiconductor substrate and gate electrode of the MOSFET upon forming the gate electrode

An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term

Abstract:  Abstract—In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960. Moreover, the power consumption can be reduced from 1.26mw to 0.37mw as well as power delay product reduced from 2.14mw*ns to 1.28mw*ns.

Thin film transistor array panel for a liquid crystal display and methods for manufacturing the same

Abstract: A black matrix having an opening at pixels of a matrix array in a display area, a common wire including common pads and common signal lines, and gate pads in a peripheral area, and an alignment key in outer area to align interlayer thin films are formed on an insulating substrate Red, blue and green color filters the edge of which overlap the black matrix are formed at the pixels on the insulating substrate, and an organic insulating layer covering the black matrix and the color filters and having a contact hole exposing the gate pad is formed thereon A gate wire including a gate line connected to the gate pad through the contact hole and a gate electrode connected to the gate line is formed on the organic insulating layer, and a gate insulating layer covering the gate wire is formed on the organic insulating layer A semiconductor pattern and ohmic contact layers are sequentially formed on the gate insulating layer of the gate electrode A data wire including a source electrode and a drain electrode that are made of a same layer on the ohmic contact layers and separated from each other, and a data line connected to the source electrode and defining the pixels of a matrix array by crossing the gate line is formed on the gate insulating layer A passivation layer covering the data wire and having contact holes exposing the gate pad and the data pad is formed, and a pixel wire including a pixel electrode, a redundant gate pad, a redundant data pad that are respectively connected to the drain electrode, the gate pad and the data pad through the contact holes

Z-source current-type inverters: digital modulation and logic implementation

Abstract: Traditionally, current source (CS) inverters have been adopted for use in medium and high power industry applications. These inverters however support only current-buck dc-ac power conversion and need a relatively complex modulator, as compared to conventional voltage source (VS) inverters. To address these limitations, this paper presents an integration of the buck-boost Z-source power conversion concept to the CS inverter topology to develop single and three-phase Z-source CS inverters. For their efficient control, the paper starts by evaluating different carrier-based reference formulations to identify different inverter state placement possibilities. The paper then proceeds to design appropriate "reference-to-switch" assignments or logic equations for mapping out the correct CS gating signals, allowing a simple carrier-based modulator to control a Z-source CS inverter with complications such as commutation difficulties and "many-to-many" state assignments readily resolved. The developed system can be implemented using a digital signal processor with an embedded pulse-width modulator and an external programmable logic device, hence offering a competitive solution for medium power single and three-phase buck-boost power conversion. Theory, simulation and experimental results are presented in the paper.