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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


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Journal ArticleDOI
TL;DR: In this paper, a 2D self-consistent Schrodinger-Poisson solver has been implemented to simulate the electrostatics of Pi-gate silicon-on-insulator (SOI) MOSFETs.
Abstract: In this paper, simulation-based research on the electrostatics of Pi-gate silicon-on-insulator (SOI) MOSFETs is carried out. To do so, a 2-D self-consistent Schrodinger-Poisson solver has been implemented. The inclusion of the quantum effects has been demonstrated to be necessary for the accurate simulation of these devices in the nanometer range. Specifically, this paper is focused on the corner effects in multiple-gate SOI MOSFETs, defined as the formation of independent channels with different threshold voltages. Corner effects are studied as a function of different parameters, such as the doping density, silicon-fin dimensions, corner rounding, and gate oxide thickness. Finally, the relation between corner effects and the transition from a fully to a partially depleted body is analyzed.

84 citations

Journal ArticleDOI
TL;DR: The proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.
Abstract: This paper presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.

83 citations

Proceedings ArticleDOI
H.L.N. Wiegman1
23 Feb 1992
TL;DR: The analysis and implementation of a resonant gate drive is discussed in this article, which is based on a simple charge pulse circuit which has conduction and logic losses and is applicable to pulse width modulation (PWM) schemes as well as resonant converters.
Abstract: The analysis and implementation of a resonant pulse gate drive are discussed. The resonant gate drive is based on a simple charge pulse circuit which has conduction and logic losses. The pulse charging and discharging instances are controlled by the user, and hence this circuit is applicable to pulse width modulation (PWM) schemes as well as resonant converters. Theoretical analysis of the circuit shows its operation. Detailed equations are presented which describe the inherent losses of the circuit. Experimental results are shown to verify the operation and loss mechanisms. >

83 citations

Journal ArticleDOI
TL;DR: In this paper, the impact of high-k gate dielectrics on device short-channel and circuit performance of fin field effect transistors is studied over a wide range of dielectric permittivities.
Abstract: The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance Cof in addition to an increase in the internal fringe capacitance Cif with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering

83 citations

Journal ArticleDOI
TL;DR: It is established that under optimized conditions, presently studied biochemical gates can be concatenated for up to order 10 processing steps and beyond that, new paradigms for avoiding noise buildup will have to be developed.
Abstract: We report an experimental evaluation of the "input-output surface" for a biochemical AND gate. The obtained data are modeled within the rate-equation approach, with the aim to map out the gate function and cast it in the language of logic variables appropriate for analysis of Boolean logic for scalability. In order to minimize "analog" noise, we consider a theoretical approach for determining an optimal set for the process parameters to minimize "analog" noise amplification for gate concatenation. We establish that under optimized conditions, presently studied biochemical gates can be concatenated for up to order 10 processing steps. Beyond that, new paradigms for avoiding noise build-up will have to be developed. We offer a general discussion of the ideas and possible future challenges for both experimental and theoretical research for advancing scalable biochemical computing.

82 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372