Topic
AND gate
About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.
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TL;DR: In this article, the first successful integration of two independent gates on a p-type FinFET was presented, to the best of our knowledge, which represents a significant performance improvement over previously reported Independent-Gate Fin-FET results.
Abstract: We present, to our knowledge, the first successful integration of two independent gates on a p-type FinFET. These results also represent a significant performance improvement over previously reported Independent-Gate FinFET results. The devices have gate lengths ranging from 0.5 to 5 /spl mu/m, and designed fin thicknesses ranging from 25 to 75 nm. Electrical results show near-ideal subthreshold slopes in double-gate mode (both gates modulated simultaneously). Independent-Gate operation is also examined by modulating saturated drain current with both front and back-gate voltages independently. The results are compiled to analyze performance trends versus fin thickness and gate length.
82 citations
TL;DR: In this paper, the work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors.
Abstract: The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.
82 citations
TL;DR: In this article, analytical models of sub-threshold current and slope for asymmetric four-terminal double-gate (DG) MOSFETs are presented, and the results of the models show excellent match with simulations using MEDICI.
Abstract: In this paper, analytical models of subthreshold current and slope for asymmetric four-terminal double-gate (DG) MOSFETs are presented. The models are used to study the subthreshold characteristics with asymmetry in gate oxide thickness, gate material work function, and gate voltage. A model for the subthreshold behavior of three-terminal DG MOSFETs is also presented. The results of the models show excellent match with simulations using MEDICI. The analytical models provide physical insight which is helpful for device design.
82 citations
Patent•
20 Mar 2008
Abstract: A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.
81 citations