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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, a modified floating-gate technique for measuring small gate currents in MOSFET's with very high resolution (0.01 fA) is described, using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFLT's.
Abstract: A modified floating-gate technique for measuring small gate currents in MOSFET's with very high resolution (0.01 fA) is described. Using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFET's. The conventional negative channel hot-electron gate oxide current is observed near V_{g} = V_{d} and a small positive gate current occurs at low V g . We argue that the dependencies of this small positive current on V g and gate length, together with results from a separate floating-source experiment, are consistent only with hot-hole injection.

81 citations

Journal ArticleDOI
TL;DR: The split-gate light emitting field effect transistors (SG-LEFET) demonstrate a new strategy for ambipolar LEFETs to achieve high brightness and efficiency simultaneously and actively and independently controlling current injection from separated gate electrodes within transporting channel.
Abstract: The split-gate light emitting field effect transistors (SG-LEFETs) demonstrate a new strategy for ambipolar LEFETs to achieve high brightness and efficiency simultaneously. The SG architecture forces largest quantity of opposite charges on Gate 1 and Gate 2 area to meet in the center of the channel. By actively and independently controlling current injection from separated gate electrodes within transporting channel, high brightness can be obtained in the largest injection current regime with highest efficiency.

81 citations

Patent
28 Sep 2004
TL;DR: In this paper, a pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor, which can act as both a leaking transistor and either a transfer gate or a reset gate.
Abstract: A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a leaking transistor and either a transfer gate or a reset gate. Alternatively, the HDR transistor may be a separate and individual transistor having the gate profile of a transfer gate or a reset gate. The leakage through the HDR transistor may be controlled by modifying the photodiode implants around the transistor, adjusting the channel length of the transistor, or thinning the gate oxide on the transistor. The leakage through the HDR transistor may also be controlled by applying a voltage across the transistor.

80 citations

Patent
20 Jun 1997
TL;DR: In this article, a carry chain multiplexer can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators, depending on the function generator.
Abstract: An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.

80 citations

Patent
11 Dec 2003
TL;DR: In this paper, the authors described a method for treating deposited gate dielectric materials, in which the deposited dielectrics is subjected to one or more non-oxidizing anneals to densify the material, one OR more oxidizing annesals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate Dielectric.
Abstract: Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.

80 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372