AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Method for fabricating metal oxide field effect transistors

Abstract: A method for fabricating a metal oxide silicon field effect transistor (MOSFET) wherein a polysilicon layer is deposited over a gate oxide film serving to insulate the gate of the MOSFET from the substrate of the MOSFET. The polysilicon layer serves to prevent the gate oxide film from being etched upon forming a gate electrode using a metal film or metal silicide side walls as a mask. Accordingly, it is possible to prevent a short circuit from occurring between the semiconductor substrate and gate electrode of the MOSFET upon forming the gate electrode.

Gate array having highly flexible interconnection structure

Abstract: A basic cell structure of a gate array that allows wiring in a macro cell is implemented solely by using first layer metallic wires and entails neither performance deterioration nor an increase in sell size. The basic cell of the gate array comprises a pMOS transistor having two FETs connected in series to each other and an nMOS transistor also having two FETs also connected in series to each other. The pMOS transistor and the nMOS transistor are formed on a substrate and arranged in parallel to each other, and gate electrodes corresponding to the FETs are commonly provided for the pMOS transistor and the nMOS transistor. In this structure, a first auxiliary wire is provided between the gate electrodes on the same layer as the gate electrodes. A second auxiliary wire is provided between adjacent basic cells also on the same layer as the gate electrodes. Wiring in a macro cell can be completed by using the first and second auxiliary wires of different types to form a two-dimensional structure. That is, wiring can be completed solely by using the first layer metallic wires.

Asymmetrical multilevel converter topology with reduced number of components

Abstract: In this study, firstly a new basic unit is proposed for multilevel converters. The proposed basic units are used as building blocks to form a cascaded multilevel converter. In other words, the proposed topology consists of cascaded basic units. The proposed basic unit and the proposed multilevel converter use lower number of switching devices and gate driver circuits. In the proposed topology, two design parameters are available: the number of cascaded basic units and the number of dc voltage sources in each basic unit. These two parameters can be used to design the desired multilevel converter based on the operational conditions. Therefore the proposed topology offers good flexibility in designing. An algorithm for determining the values of the dc voltage sources is given in order to generate maximum number of voltage levels. The comparison results with some recently introduced topologies show that the proposed topology effectively reduces the components count. The simulation results obtained in PSCAD/EMTDC as well as the experimental results of a 51-level inverter based on the proposed topology are presented to verify its performance.

A spin-wave logic gate based on a width-modulated dynamic magnonic crystal

Abstract: An electric current controlled spin-wave logic gate based on a width-modulated dynamic magnonic crystal is realized. The device utilizes a spin-wave waveguide fabricated from a single-crystal Yttrium Iron Garnet film and two conducting wires attached to the film surface. Application of electric currents to the wires provides a means for dynamic control of the effective geometry of the waveguide and results in a suppression of the magnonic band gap. The performance of the magnonic crystal as an AND logic gate is demonstrated.

High-voltage circuit for insulated gate field-effect transistor

Abstract: A high-voltage circuit for insulated gate field-effect transistors (MOSFETs) is provided wherein two MOSFETs are connected in series, the source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the high-voltage circuit, the drain of the second MOSFET being used as a drain terminal of the circuit. First and second resistors are connected in series between the source terminal and the drain terminal, and a biasing voltage supply is connected between the juncture of both the resistors and the gate of the second MOSFET. By virtue of these connections the "on" resistance of the high-voltage circuit is improved due to the effect of the biasing voltage effect in bringing the second MOSFET into an "on" condition.