AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

A compact GaN-based DC-DC converter IC with high-speed gate drivers enabling high efficiencies

Abstract: In this paper, we present a novel compact DC-DC converter IC in which normally-off GaN-GITs (Gate Injection Transistors) and gate drivers are integrated into one chip. The DC-DC converter IC can achieve higher efficiency and smaller chip size by reducing parasitic inductances between switching power devices and gate drivers. The gate driver, having a DCFL (Direct Coupled FET Logic) with a buffer amplifier which is consisted of a GaN-HFET (Hetero-junction FET) and GaN-GITs can operate with higher speed and lower power consumption. The fabricated DC-DC converter IC exhibits a peak efficiency as high as 86.6% at 2MHz for the 12V-1.8V conversion.

Method of fabricating power rectifier device to vary operating parameters and resulting device

Abstract: A semiconductor rectifying device which emulates the characteristics of a low forward voltage drop Schottky diode and which is capable of a variety of electrical characteristics from less than 1 A to greater than 1000 A current with adjustable breakdown voltage. The manufacturing process provides for uniformity and controllability of operating parameters, high yield, and readily variable device sizes. The device includes a semiconductor body with a guard ring on one surface to define a device region in which are optionally formed a plurality of conductive plugs. Between the guard ring and the conductive plugs are a plurality of source/drain, gate and channel elements which function with the underlying substrate in forming a MOS transistor. The channel regions are defined by using the photoresist mask for the gate oxide with the photoresist mask isotropically etched to expose a peripheral portion of the gate oxide (and gate electrode) with ions thereafter implanted through the exposed gate for forming the channel region. The source/drain (e.g. source) regions can be formed by ion implantation or by out-diffusion from a doped polysilicon layer.

Limits of gate-oxide scaling in nano-transistors

Abstract: This paper explores the ultimate scaling limit of gate oxide due to MOSFET gate leakage and device performance. The limit on Tox reduction with respect to gate leakage tolerance is considered by the concept of "dynamic" gate leakage in nano-scale MOSFET's. Tox scaling is also limited by transistor performance degradation due to the loss of inversion layer charge through gate leakage and the degradation of carrier mobility in the channel from increased scattering. All the three effects are investigated experimentally on CMOS devices with gate length down to 50 nm and gate Tox down to 12 A. The minimum Tox is proposed and the implications on voltage scaling, high-k gate dielectrics and low-temperature CMOS are discussed.

Tri-gate and gate around MOSFET devices and methods for making same

Abstract: A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gate formed on top of the fin structure. A gate around MOSFET includes multiple fins, a first sidewall gate structure formed adjacent one of the fins, a second sidewall gate structure formed adjacent another one of the fins, a top gate structure formed on one or more of the fins, and a bottom gate structure formed under one or more of the fins.