AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Mosfet logic inverter for integrated circuits

Abstract: The specification discloses a logic inverter comprised of a depletion mode MOSFET used as a resistive load between a drain supply voltage and an output and one or more enhancement mode MOSFET''s connected between output and source supply voltage. The source and gate of the depletion mode device are electrically common, and the gates of the enhancement mode devices form the logic inputs. The use of one enhancement mode device provides a simple inverter, a plurality of enhancement mode devices in parallel form a NOR gate, and a plurality of enhancement mode devices in series form a NAND gate. Combination NOR and NAND GATES may also be formed. The basic inverter circuit is also combined with a push-pull output stage to provide increased speed of operation, particularly at higher drain supply voltages. Still another embodiment utilizes an enhancement mode transistor connected between the depletion mode transistor and the output of the basic inverter stage to provide a disable function in which output drain current is switched off under all logic input conditions.

A Programmable Logic Approach for VLSI

Abstract: This paper explores the use of a proposed programmable storage/logic array (SLA) chip as a general purpose universal logic element for digital computers. The SLA is compared to other programmable logic arrays in implementation and utilization, showing how it permits construction of complete digital subsystems on one chip without sacrifice in programmability. When compared with other contending very large-scale integrated technology (VLSI) approaches, such as microprogrammed processors and gate arrays, the SLA offers an attractive combination of cost, performance, and ease of implementation.

Design and synthesis of a novel PET and ICT based 1,8-naphthalimide FRET bichromophore as a four-input Disabled-Enabled-OR logic gate

Abstract: The synthesis, sensor activity and logic behavior of a novel donor–acceptor system based on ICT and PET 1,8-naphthalimide fluorescent probes is reported. The system was configured on the “fluorophore1–receptor1–fluorophore2–spacer–receptor2” model where the two probes are integrated in a logic circuit comprising a FRET bichromophoric system with multilevel fluorescent output. The synthesized compound shows colorimetric and fluorescence signaling properties as a function of pH and in the presence of transition metal ions with emphasis on Cu2+ and Pb2+. Due to the remarkable fluorescence and absorption changes in the presence of protons, hydroxide anions, Cu2+ and Pb2+ ions the novel system executes four-input Disabled–Enabled-OR logic gate as well as two-input INHIBIT and IMPLICATON logic gates and is able to act as a three output combinatorial logic circuit with four chemical inputs. Due to the parallel action of four-input input4-Disabled-input3-Enabled-OR logic gate (Output 1) with INHIBIT (Output 2) and IMPLICATON (Output 3) gates, the system can be switched over Disable and Enable mode reversible.

Realizing lateral wrap-gated nanowire FETs: Controlling gate length with chemistry rather than lithography

Abstract: An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for vertically oriented nanowire transistors. We report a method for producing laterally oriented wrap-gated nanowire field-effect transistors that provides exquisite control over the gate length via a single wet etch step, eliminating the need for additional lithography beyond that required to define the source/drain contacts and gate lead. It allows the contacts and nanowire segments extending beyond the wrap-gate to be controlled independently by biasing the doped substrate, significantly improving the sub-threshold electrical characteristics. Our devices provide stronger, more symmetric gating of the nanowire, operate at temperatures between 300 to 4 Kelvin, and offer new opportunities in applications ranging from studies of one-dimensional quantum transport through to chemical and biological sensing.

GaAs LSI-directed MESFET's with self-aligned implantation for n + -layer technology (SAINT)

Abstract: Self-aligned implantation for n+-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET's to be used in LSI's. This technology has made it possible to arbitrarily control the spacing between the n+-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FET's with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-law I - V fitting has been improved by a factor of 3.4, compared to conventional FET's without the n+-layer. Thermal emission for carriers from the source n+-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FET's is definitely smaller than that for [011] gate FET's. The threshold-voltage standard deviations for [011] gate FET's with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.