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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the authors presented a new configuration of all-optical AND gate based on two-dimensional photonic crystal composed of Si rods in air, and two AND gate structures with and without probe input are proposed.
Abstract: We present a new configuration of all-optical AND gate based on two-dimensional photonic crystal composed of Si rods in air. Two AND gate structures with and without probe input are proposed. The proposed structures are designed with T-shaped waveguide without using nonlinear materials and optical amplifiers. The performance of the proposed AND gate structures is analyzed and simulated by plane-wave expansion and finite difference time domain methods. The AND gate without probe input needs only one T-shaped waveguide, whereas the AND gate with probe input needs two T-shaped waveguides. The former AND gate offers a bit rate of 6.26 Tbps with a contrast ratio of 5.74 dB, whereas the latter AND gate offers a bit rate of 3.58 Tbps whose contrast ratio is 9.66 dB. It can be expected that these small size T-shaped structures are suitable for large-scale integration and can potentially be used in on-chip photonic integrated circuits.

64 citations

Patent
10 Oct 2001
TL;DR: In this paper, a gate is formed in a partial area of the surface of a semiconductor substrate, and on this gate insulating film, a gate electrode is formed, conformable to the side wall and the surface.
Abstract: A gate insulating film is formed in a partial area of the surface of a semiconductor substrate, and on this gate insulating film, a gate electrode is formed. An ONO film is formed on the side wall of the gate electrode and on the surface of the semiconductor substrate on both sides of the gate electrode, conformable to the side wall and the surface. A silicon nitride film of the ONO film traps carriers. A conductive side wall spacer faces the side wall of the gate electrode and the surface of the semiconductor substrate via the ONO film. A conductive connection member electrically connects the side wall spacer and gate electrode. Source and drain regions are formed in the surface layer of the semiconductor substrate in areas sandwiching the gate electrode. A semiconductor device is provided which can store data of two bits in one memory cell and can be driven at a low voltage.

64 citations

Journal ArticleDOI
TL;DR: In this paper, the authors combine mechanistic-kinetic models and stochastic simulation techniques as well as the techniques of in vivo molecular biology to study the potential of a synthetic, single promoter AND gate.

64 citations

Proceedings ArticleDOI
15 Jul 2009
TL;DR: This paper presents the efficient approaches for designing reversible fast adders that implement carry look-ahead and carry-skip logic and demonstrates that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.
Abstract: Irreversible logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit naturally takes care of heating because it implements only the functions that have one-to-one mapping between its input and output vectors. Therefore reversible logic design becomes one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient approaches for designing reversible fast adders that implement carry look-ahead and carry-skip logic. The proposed 16-bit high speed reversible adder will include IG gates for the realization of its basic building block. The IG gate is universal in the sense that it can be used to synthesize any arbitrary Boolean-functions. The IG gate is parity preserving, that is, the parity of the inputs matches the parity of the outputs. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Therefore, the proposed high speed adders will have the inherent opportunity of detecting errors in its output side. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

64 citations

Journal ArticleDOI
TL;DR: In this article, an all-optical flexible 20-Gb/s logic and gate based on cascaded sum-and difference-frequency generation in a periodically poled lithium niobate waveguide is proposed and experimentally demonstrated.
Abstract: All-optical flexible 20-Gb/s logic and gate based on cascaded sum- and difference-frequency generation in a periodically poled lithium niobate waveguide is proposed and experimentally demonstrated. The theoretical analyses further indicate that 40-, 80-, and 160-Gb/s ultrahigh-speed logic and operations can potentially be performed. Moreover, it is expected that the and output can be tuned in a wide wavelength range (67 nm) with slight fluctuation of the Q-factor and extinction ratio.

63 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372