Topic
AND gate
About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.
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TL;DR: In this article, an all-optical logic AND gate is demonstrated using a semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI).
62 citations
Patent•
05 Nov 1991TL;DR: In this paper, the gate of the FET is connected to an output of the local oscillator matching network and the source of the source is connected with an input of the IF filter.
Abstract: A mixer includes a local oscillator (LO) matching network having an LO input port, an RF matching network also having an input port and an IF filter which provides an IF output from the mixer. A FET having a gate, drain and source operates at the center of the mixer. A resonant loop is connected between the drain and gate of the FET. The gate of the FET is connected to an output of the LO matching network. The drain of the FET is connected to an output of the RF matching network. The source of the FET is connected to an input of the IF filter. The resonant loop may incorporate a DC blocking capacitor which does not function as part of the resonant loop, but which serves to block DC allowing the drain and gate of the FET to be biased independently.
62 citations
TL;DR: Evidence of a systematic and sizable response enhancement for an OTFT sensor operated in the enhanced mode is presented, most likely as a result of a trapping or of a doping process of the organic active layer.
62 citations
Patent•
30 Apr 1992TL;DR: In this article, the authors proposed a method of forming a vertical transistor device, which comprises: forming a n-type source layer 12, forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a drain layer 16 over the gate structure to provide a buried carbon-doped gate structure with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage.
Abstract: This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.
61 citations
01 Sep 2012
TL;DR: In this article, the high-temperature performance of the commercial SiC power MOSFETs has been extensively evaluated beyond 125 °C -the maximum junction temperature according to the datasheet.
Abstract: In this paper, the high-temperature performance of the commercial SiC power MOSFETs has been extensively evaluated beyond 125 °C - the maximum junction temperature according to the datasheet. Both the static and switching characteristics have been measured under various temperatures up to 200 °C. The results show the superior electrical performance of the SiC MOSFETs for high-temperature operation. Meanwhile, the gate biasing and gate switching tests have also been conducted to test the gate oxide reliability of these devices under elevated temperatures. The test results reveal the degradation in the device characteristics under high temperature and different gate voltage conditions, which exhibit the trade-off between the performance and the reliability of SiC MOSFETs for high-temperature applications.
61 citations