AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Method for forming field effect transistor having multiple gate electrodes surrounding the channel region

Abstract: A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

Semiconductor device having both memory and logic circuit and its manufacture

Abstract: A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned. In this case, the silicon film is patterned to leave word lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area. Source/drain regions of MISFET's are formed in a surface layer of the semiconductor substrate by doping impurities into regions on both sides of each word line in the memory cell area and into regions on both sides of each gate electrode in the logic circuit. The electrical characteristics of the logic circuit area can be improved while the data storage characteristics of memory cells are maintained good.

CMOS technology for MS/RF SoC

Abstract: Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered to be roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF system-on-chip (SoC) technology from a scaling perspective. The paper also discusses the implications that physical phenomena such as mechanical stress and gate leakage as well as gate patterning have on technology definition and characterization.

Postlayout logic restructuring using alternative wires

Abstract: In this paper, we propose a layout-driven synthesis approach for field programmable gate arrays (FPGA's). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuit's functionality. Allowing the logic blocks to have alternative functions also increases the chance of successful routing. A redundancy addition and removal technique is used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

Self-aligned transistor with sidewall base electrode

Abstract: A multiple self-aligned structure that facilitates high packing density and high speed in bipolar VLSI's is proposed. The device has polysilicon sidewall base electrodes to reduce parasitic junction capacitances. The new devices indicate that capacitances between the base and collector regions are reduced to 1\4 and the ratio of reverse-to-forward current gain is increased about 5 times that of conventional bipolar transistor structures, and gate delay in IIL circuits is about 1 ns/gate. The structure opens the way for further scaled-down VLSI.