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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


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Patent
26 May 1994
TL;DR: In this paper, the authors present a logic synthesis tool that performs a timing analysis during the optimization of a hardware description file including general logic expressions of a prototype circuit by minimizing a delay value for a gate network comprised of logic cells provided in a target library.
Abstract: A computer automated logic synthesis tool performs a timing analysis during the optimization of a hardware description file including general logic expressions of a prototype circuit by minimizing a delay value for a gate network comprised of logic cells provided in a target library. Minimization occurs by modeling a gate network for a logic expression that orders the input signals into the gate network according to their input delays, and the output delays from assigned logic cells. The output delay for the assigned logic cell is based on intrinsic delays of boolean nodes in the logic cells. The delay for the gate network includes an R-C delay value for gate fan-out, based on the average R-C delay values in the target library. The logic synthesis tool is able to select from among various alternate logically equivalent gate networks, the gate network that provides the minimized timing delay.

57 citations

Patent
06 May 1994
TL;DR: In this article, an EEPROM cell with a first MOS transistor formed in a semiconductor substrate of a first conductivity type and having current conducting regions of a second conductivities type and a gate electrode, a well of another conductivities provided in the substrate, a plate electrode formed on the well with an insulating layer interposed there between, and at least one region of the first conductivities Type formed in the well adjacent to the plate electrode.
Abstract: Disclosed is an EEPROM cell which can be manufactured with ease by the standard CMOS process. The EEPROM cell of the present invention has a first MOS transistor formed in a semiconductor substrate of a first conductivity type and having current conducting regions of a second conductivity type and a gate electrode, a well of a second conductivity type provided in the substrate, a plate electrode formed on the well with an insulating layer interposed therebetween, and at least one region of the first conductivity type formed in the well adjacent to the plate electrode. The gate electrode and the plate electrode are connected in common and act as a floating gate, and the well acts as a control gate.

57 citations

Patent
30 Jul 1998
TL;DR: In this paper, the gate array type semiconductor device achieves high-speed operation and low power consumption by forming body contact regions to divide source/drain layers and forming gate electrodes to sandwich gate insulating films there between.
Abstract: In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption. Further, with positional relation between the body contact regions (9), (10) and the gate contact regions (5), (7), the device is capable of freely setting the transistors to be of either a gate control type or a gate fixed type. As a result, the gate array type semiconductor device achieves high-speed operation and low power consumption.

57 citations

Journal ArticleDOI
TL;DR: In this paper, a high contrast (5:1), 1.3 μm wavelength optical and gate is demonstrated using a bistable Fabry-Perot InGaAsP/InP laser amplifier with large gain.
Abstract: A high contrast (5:1), 1.3 μm wavelength optical and gate is demonstrated using a bistable Fabry–Perot InGaAsP/InP laser amplifier with large gain. Using simple arguments, it is shown that, subject to realistic constraints, the maximum attainable contrast ratio in a bistable Fabry–Perot logic gate is about 10. Unlike bistable amplifiers, there is a significant trade‐off between contrast and gain in passive devices.

57 citations

Patent
07 Feb 2008
TL;DR: In this paper, a non-volatile memory cell capable of byte rewriting, having an excellent tolerance of rewriting, and being a multi-storage configuration is constructed, where a memory gate electrode is formed via a gate insulation film and gate nitride film.
Abstract: PROBLEM TO BE SOLVED: To comparatively easily manufacture a non-volatile memory cell capable of byte rewriting, having an excellent tolerance of rewriting, and being a multi-storage configuration. SOLUTION: On a first semiconductor area (30), a memory gate electrode (33) is formed via a gate insulation film (31) and gate nitride film (32). On both sides thereof, a first and second switch gate electrodes (36, 37) and first and second signal electrodes (38, 39), that are source/drain electrodes, are formed and a non-volatile memory cell is constituted. Then, with the memory gate electrode being a mask, a high concentration impurity is introduced into the first semiconductor area just under the memory gate electrode. COPYRIGHT: (C)2008,JPO&INPIT

57 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372