AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Comparison of gate and drain current detection of hydrogen at room temperature with AlGaN∕GaN high electron mobility transistors

Abstract: Pt-gated AlGaN∕GaN high electron mobility transistors can be used as room-temperature hydrogen gas sensors at hydrogen concentrations as low as 100ppm. A comparison of the changes in drain and gate current-voltage (I-V) characteristics with the introduction of 500ppm H2 into the measurement ambient shows that monitoring the change in drain-source current provides a wider gate voltage operation range for maximum detection sensitivity and higher total current change than measuring the change in gate current. However, over a narrow gate voltage range, the relative sensitivity of detection by monitoring the gate current changes is up to an order of magnitude larger than that of drain-source current changes. In both cases, the changes are fully reversible in <2–3min at 25°C upon removal of the hydrogen from the ambient.

Voltage-switchable photocurrents in single-walled carbon nanotube-silicon junctions for analog and digital optoelectronics

Abstract: A photodiode-based logic device employing scalable heterojunctions of carbon nanotubes and silicon whose output currents can be manipulated by both optical and electrical inputs is developed Bidirectional phototransistors and novel clock-triggerable logic elements, such as a mixed optoelectronic AND gate, a 2-Bit optoelectronic ADDER/OR gate and a 4-Bit optoelectronic D/A converter, are also demonstrated

Vertical nanowire transistor with axially engineered semiconductor and gate metallization

Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length

Novel forksheet device architecture as ultimate logic scaling device towards 2nm

Abstract: To compensate for expected gate pitch scaling slowdown below 42nm, several scaling boosters are needed to reduce the logic standard cell height (CH). However, limited scaling benefits can be achieved using FinFET and Gate all around (GAA) nanosheets (NSHs) due integration limits in achieving tight PMOS to NMOS (PN) separation. Therefore, a novel forksheet (FSH) device architecture is proposed achieving extremely scaled PN space using limited additional processing complexity. The FSH achieves 10% frequency increase at iso-power and 24% power reduction at iso-frequency compared to GAA nanosheet with a combined area scaling of 20%. SRAM bit cell area scaling of 30% and read delay performance increase is shown.

Non-volatile devices, and electronic systems comprising non-volatile devices

Abstract: The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The source/drain regions can extend into the Si/Ge. The memory or logic devices further include an insulative material over the floating gate or plate, and a control gate separated from the floating gate or plate by the insulative material. The crystalline Si/Ge can have a relaxed crystalline lattice, and a crystalline layer having a strained crystalline lattice can be formed between the relaxed crystalline lattice and the floating gate or plate. The devices can be fabricated over any of a variety of substrates. The floating plate option can provide lower programming voltage and orders of magnitude superior endurance compared to other options.