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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the gate leakage currents of single-gate silicon-on-insulator (SOI) n-type MOSFETs are investigated, assuming direct tunneling as the leakage mechanism and using either a 1-D Schrodinger-Poisson-based approach coupled to the conventional drift-diffusion transport model or a full quantum mechanical treatment.
Abstract: The gate leakage currents of single-gate silicon-on- insulator (SOI) n-type MOSFETs are investigated, assuming direct tunneling as the leakage mechanism and using either a 1-D Schrodinger-Poisson-based approach coupled to the conventional drift-diffusion transport model or a full quantum mechanical treatment. The first approach consists of calculating the transmission probability through the dielectric material along straight lines connecting the transistor channel to the gate. The second method is based on a 2-D Schrodinger-Poisson solver, where carriers are injected into the device from the source, drain, and gate contacts. The simulated structures have a physical gate length of 32 nm. The channel is isolated from the gate contact by a dielectric layer with an equivalent oxide thickness of 1.2 nm. This layer is composed of either pure SiO2 or a high-kappa SiO2 - HfO2 stack. Irrespective of the dielectric material, the leakage currents calculated with the 1-D approach are about one order of magnitude smaller at low gate voltages and converge toward the same value as the channel potential barrier decreases. The difference is caused by the diffraction of the electron waves at both edges of the gate contact. This peculiar 2-D behavior of the gate leakage currents, as well as the limit of the 1-D model, is discussed in this paper for various dielectric configurations.

47 citations

Patent
10 Oct 1991
TL;DR: In this paper, the authors proposed a third phase to store data, which allows domino logic gates (1, 2, 3) to be cascaded and pipelined without intervention latches.
Abstract: CMOS domino logic is normally used only in two phases: precharge and logic evaluation. The invention uses a third phase to store data, which allows domino logic gates (1, 2, 3) to be cascaded and pipelined without intervention latches. The inputs (Data In) to this system must have strictly monotonic transitions during the logic evaluation phase and the precharge signal must be active during only the precharge phase. Furthermore, the pipelined system can feed its output back to the input to form an iterative structure. Such a feedback pipeline is viewed as a ''loop'' or ''ring'' of logic which circulates data until the entire computation is complete.

47 citations

Journal ArticleDOI
TL;DR: In this article, a new analytical approach is proposed to extract the gate dependent threshold voltage for cylindrical gate tunnel FETs (CG-TFETs) by using peak transconductance change method based on the saturation of tunneling barrier width.

47 citations

Book ChapterDOI
01 Jan 2003
TL;DR: In this article, a low-order Class-E power amplifier with a load-network loaded Q (Q L ) was presented, and the output power was 38% to 10% less than expected, for Q L values in the usual range of 1.8 to 5.
Abstract: Class-E power amplifiers [1]–[6] achieve significantly higher efficiency than for conventional Class-B or -C. Class E operates the transistor as an on/off switch and shapes the voltage and current waveforms to prevent simultaneous high voltage and high current in the transistor; that minimizes the power dissipation, especially during the switching transitions. In the published low-order Class-E circuit, a transistor performs well at frequencies up to about 70% of its frequency of good Class-B operation (an unpublished higher-order Class-E circuit operates well up to about double that frequency). This paper covers circuit operation, improved-accuracy explicit design equations for the published low-order Class E circuit, optimization principles, experimental results, tuning procedures, and gate/base driver circuits. Previously published analytically derived design equations did not include the dependence of output power (P) on load-network loaded Q (Q L ); as a result, the output power was 38% to 10% less than expected, for Q L values in the usual range of 1.8 to 5. This paper includes an accurate new equation for P that includes the effect of Q L .

47 citations

Journal ArticleDOI
TL;DR: In this paper, a biomolecular AND gate function with double sigmoid response (sigmoid in both inputs) was realized, where two enzyme biomarker inputs activate the gate output signal, which can then be used as indicating liver injury.
Abstract: We report the first realization of a biomolecular AND gate function with double-sigmoid response (sigmoid in both inputs). Two enzyme biomarker inputs activate the gate output signal, which can then be used as indicating liver injury, but only when both of these inputs have elevated pathophysiological concentrations, effectively corresponding to logic-1 of the binary gate functioning. At lower, normal physiological concentrations, defined as logic-0 inputs, the liver-injury output levels are not obtained. High-quality gate functioning in handling of various sources of noise, on time scales of relevance to potential applications, is enabled by utilizing “filtering” effected by a simple added biocatalytic process. The resulting gate response is sigmoid in both inputs when proper system parameters are chosen, and the gate properties are theoretically analyzed within a model devised to evaluate its noise-handling properties.

47 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372