Showing papers on "Anodic bonding published in 1988"

Bonding of silicon wafers for silicon‐on‐insulator

Abstract: Several aspects of a new silicon‐on‐insulator technique utilizing bonding of oxidized silicon wafers were investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces contacted face‐to‐face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60–85 erg/cm2 at room temperature to ≂2200 erg/cm2 at 1400 °C. The strength was essentially independent of the bond time. Bonds created during 10‐s annealing at 800 °C were mechanically strong enough to withstand the mechanical and/or chemical thinning of the top wafer to the desired thickness and subsequent device processing. A model was proposed to explain three distinct phases of bonding in the temperature domain. Electrical properties of the bond were tested using metal‐oxide‐semiconductor (MOS) capacitors. The results were consistent with a negative charge de...

Silicon fusion bonding for pressure sensors

Abstract: Two novel processes for fabricating silicon piezoresistive pressure sensors are presented. The chips described are used to demonstrate an important silicon/silicon bonding technique called silicon fusion bonding (SFB). Using this technique, single-crystal silicon wafers can be reliably bonded with near-perfect interfaces without the use of intermediate layers. Pressure transducers fabricated with SFB exhibit greatly improved performance over devices made with conventional processes. SFB is also applicable to many other microchemical structures. >

Bubble-Free Silicon Wafer Bonding in a Non-Cleanroom Environment

Abstract: Bubble-free bonding of 4-inch silicon wafers on either silicon or quartz wafers is achieved outside a cleanroom. Two wafers are stacked horizontally in a rack with the two mirror-polished surfaces facing each other. In order to avoid wafer contact during hydrophilization, cleaning, and drying, the wafers are separated in the rack by teflon spacers introduced at the wafer edges. After drying the wafers by a spin dryer, the spacers are removed and bonding occurs. Using this procedure we are also able to monitor the bonding process between quartz and silicon wafers at different temperatures. We find that the initial wafer bonding process at room temperature stops operating at temperatures above 200°C.

A method for manufacturing semiconductor absolute pressure sensor units

Abstract: A method for manufacturing semiconductor absolute pressure sensor units includes anodically bonding a silicon sensor wafer (10) and a silicon cap wafer (12) with a borosilicate glass layer (32) disposed therebetween so as to surround respective sensor chips on the silicon sensor wafer (10) by introducing a matrix shaped conductive layer (28) in contact with and in alignment with the borosilicate glass layer (32), the matrix shaped conductive layer (28) is used as a negative electrode during anodic bonding operation so that a high bonding strength is obtained and sodium ions contained in the borosilicate glass layer (32) are kept away from bond regions after completing the anodically bonding operation.

Semiconductor device in which wiring layer is formed below bonding pad

Abstract: In a semiconductor device wherein a bonding pad (22 or 23) is formed on an electrode (17-1 to 17-8, or 18-1 to 18-8) through an insulating interlayer (19) and a bonding wire (25 or 26) is bonded to the bonding pad (22 or 23) by thermocompression bonding, a through hole (21-1 to 21-4, or 20-1 to 20-3) for connecting the bonding pad (23 or 22) and the electrode (17-4 to 17-7, or 18-1 to 18-3) is formed in the insulating interlayer (19) above a contact hole (15-1 to 15-7, or 16-1 to 16-8) for connecting the electrode (17-1 to 17-8, or 18-1 to 18-8) and an active region (13-1 to 13-7, or 12) formed in a semiconductor substrate (11). Metal columns of members of the electrode (17-4 to 17-7, or 18-1 to 18-3) filled in the contact hole (15-4 to 15-7, or 16-1 to 16-3) and members of the bonding pad (23 or 22) filled in the through hole (20-1 to 20-3, or 21-1 to 21-4) are formed under the bonding pad (23 or 22).

Mechanisms of anodic bonding of silicon to pyrex glass

Abstract: The mechanisms of formation of anodic bonds between glasses and metals are examined. The process is found to be an electrochemical analog to thermal glass-to-metal seals, where the metal surface is oxidized into the glass due to the development of large electric fields across the anodic depletion layer. The current vs. time transient at constant voltage contains a significant amount of information regarding the process mechanisms, which are predominantly electrochemical. >

Method for fabricating a silicon carbide substrate

Abstract: Two realizations of a method are disclosed for fabricating semiconductor substrate having an S0I β -SiC on insulator structure. In the first realization, two substrates are prepared. The first substrate is silicon coated with SIO₂ ; the second substrate is silicon on which β -SiC is hetero-epitaxially grown. These substrates are bonded to each other by a heating process. During the heating process, anodic bonding may be applied. The bonded substrate is then etched or mechanically polished off from the side of the second substrate, to expose the β -SiC layer. In the second realization, β -SiC is grown on a silicon substrate. The surface of the substrate is coated with SiO₂ ; then polysilicon or poly-SiC is deposited on the surface of the β-SiC side. The substrate is then etched or mechanically polished from the side of the silicon substrate to expose the β -SiC.

Silicon and silicon dioxide thermal bonding for silicon‐on‐insulator applications

Abstract: There has been a good deal of interest recently in the applicability of thermal bonding to silicon‐on‐insultator (SOI) technology. Thermal bonding (also called direct bonding) is accomplished by mating polished, properly hydrolyzed silicon and/or silicon dioxide surfaces, which are then annealed to promote diffusion bonding. In order to produce high‐quality SOI layers it must be demonstrated that the interface betweeen the wafers is void‐free over the entire surface of the wafer (4‐in. wafers in our study). We have found that the standard annealing step which has been used by other groups to form the wafer bond must be followed by a hyperbaric, high‐temperature annealing cycle in order to produce interfaces which are completely void‐free. In addition, we have found that mating the wafers in a controlled atmosphere is necessary to insure that voids do not remain after the thermal processing is complete. We shall present transmission electron micrographs which reveal the morphology of the bonded interface on an atomic scale. We shall submit C‐scan acoustic micrographs and infrared transmission thermographs which display the areal nature of the bonding voids.

A new LSI bonding technology 'Micron bump bonding assembly technology'

Abstract: A novel LSI chip bonding method called the micro-bump bonding method was developed for direct bonding between the large-scale integrated (LSI) electrode and the electrode provided on the circuit substrate In this method, the shrinkage stress generated in light-setting insulating resin results in a compressive force on the LSI chip against the electrodes on the substrate LSI chips having an interelectrode spacing of 10 mu m and 2320 electrodes in total were successfully gang bonded in a face-down form with high reliabilities >

Method of bonding a microelectronic device

Abstract: A method for ball-bonding thin film structures. The bonding characteristics of a thin-film electrode structure are measured, before the actual bonding step, by pressing a ball (of a material similar to that of the bonding wire) against an electrode by a bonding capillary, and then measuring the resultant indentation of the electrode. The depth of this test indentation of the electrode has a good correlation with the bondability.

Lead frame for a semiconductor device

Abstract: A lead frame for a semiconductor device includes a metal strip made of copper or copper alloy having a plurality of wire bonding areas to which metal wires are directly connected by a direct bonding method. The wire bonding areas are electroplated with a thin silver film or a palladium film, so that formation of a copper oxidized film on the wire bonding area is substantially prevented.

Controlled compression furnace bonding

Abstract: Disclosed is a system and method for controlled compression furnace bonding of a semiconductor chip to conductive elements of a leadframe. The system comprises a holding member having a chip support surface for supporting a semiconductor chip and a positioning system for precisely positioning conductive elements of a leadframe with corresponding bonding locations on the semiconductor chip. A furnace heating system comprising a furnace is employed for heating and bonding the conductive elements to the chip bonding locations. The method invention comprises positioning a semiconductor chip comprising a plurality of bonding locations in a holding member with a chip support surface; providing performed bonding material for connecting conductive elements of a leadframe with the chip bonding locations; aligning the conductive elements of a leadframe with corresponding bonding locations on the semiconductor chip; moving the leadframe conductive elements toward the chip bonding locations so that the bonding material is aligned with the conductive elements in the chip bonding locations; furnace bond heating the bonding material to a point of reflow; and cooling the bonding material to complete the bonding process between the leadframe conductive elements and the corresponding chip bonding locations.

A new silicon-on-glass process for integrated sensors

Abstract: A process is reported for the formation of high-performance thin single-crystal silicon films on glass substrates. The process utilizes the electrostatic bonding of a silicon wafer to glass and subsequent etching of the silicon to form films having thickness controlled from less than 2 mu m to over 20 mu m. The use of Corning 1729 glass substrates yields an excellent thermal expansion match to the silicon film and allows the use of postbond processing temperatures for the films of as high as 800 degrees C, allowing the formation of both MOS and bipolar device structures. Thus, integrated circuitry can be incorporated in dissolved-wafer sensing structures. A variety of related processes are also possible where some or all of the silicon device processing is performed at high temperature before bonding to the glass. >

Bonding method for bumpless beam lead tape

Abstract: A tape automated bonding method and structure is disclosed. Interconnection using prepatterned metal beam tape interconnect is accomplished by providing vias in passivation layers overlaying a metal region in or on the major surface of the device which is to receive the interconnect leads, eliminating the requirement for bonding pad bumps. Ultrasonic pressure is applied to the beams as they superpose the vias, bonding each lead to its respective metal region.

Ceramic-metal joining

Abstract: A method for improving the reliability of a ceramic-metal joint by reducing the dynamic mismatch stresses and strains on the ceramic due to the mismatch in thermal expansions of the two materials. This is done by bonding with a metal layer the ceramic to metal to form a bonding interfacial region between the ceramic and metal; and radially grading the interface region the thermal conductivity, thermal expansion coefficient, or tensile strength of the metal layer. An article in the form of a laterally graded, metallic bonding disc for overcoming problems of dynamic mismatch stresses and strains is also disclosed and claimed.

Process of wire bonding for semiconductor device

Abstract: For preventing a semiconductor device from separation of a passivation film, there is disclosed a process of wire bonding comprising the steps of: (a) preparing an intermediate structure of a semiconductor device; (b) forming an inter-level insulating layer of an organic material on the intermediate structure; (c) forming at least one bonding pad on the inter-level insulating layer; (d) growing a passivation film of an inorganic material on the inter-level insulating film in a high temperature ambient, the passivation film exposing the bonding pad; and (e) connecting a bonding wire to the bonding pad at a temperature lower than that of the high temperature ambient

Bonding composition for ceramics comprising metal oxide melt and method for bonding ceramics

Abstract: A bonding composition comprising a metal oxide melt comprising (a) CaO, (b) SiO2 and/or Al2 O3, and (c) a metal oxide selected from TiO2, ZrO2, Cr2 O3, HfO2, Nb2 O3 and Ta2 O5 is melt-bonded on the surface of a ceramic material, and the ceramic material is bonded to an adherend, if necessary through at least one layer selected from a plating layer, a solder layer, and a buffer layer. In this manner, a strong bonding can be very easily obtained.

Sealing glass for matched sealing of copper and copper alloys

Abstract: The present invention relates to a glass for making glass to metal seals. The coefficient of thermal expansion of the glass is in excess of 160×10 -7 in/in/°C. making the glass particularly useful for sealing copper and copper based alloys. The glass has particular utility in the manufacture of electronic packages and multi-layer circuitry.

Oxide coatings for fluoride glass

Abstract: Heavy metal fluoride glass optical fiber with or without a cladding and coated with an outer layer of an oxide glass having a glass transition temperature of less than 300°C and a thermal expansion coefficient of between 15 and 19 x 10-6°C-1. Also, a method of making and providing such coatings on fluoride glass, and fiber optic products prepared by such methods.

Method of manufacturing article including melting thermosetting-powder

Abstract: Manufacture of an article incorporating a thermosetting-powder surface-coating includes bonding a component to the article to the coating by contacting the melted powder with the component before curing takes place, and maintaining it in contact through curing. In a glass architectural panel, an aluminium foil is bonded in this way to a polyester/triglycidylisocyanurate powder coating on the silane-primed back of the facing glass; the metal foil is backed by a plastics or rubber open-cell material to enhance resistance of the glass to impact, and also, together with the foil, resistance to thermal shock. The coating includes pigmentation to give the effect of colored glass, or is clear to allow the contact-surface of the metal to show through; further decorative effect is obtained by pigmentation variation in the coating and/or partial metallization of the glass back-surface. The technique is also applied to bonding fittings to the powder-coated face of a door; of decals of cured powder-coating material to, or within, powder-coatings; of glass over apertures in metal walls; and of glass to glass in building up a laminate.

Direct glassing of silicon solar cells

Abstract: An alternate method of attaching coverglasses to silicon solar cells-currently achieved using silicone adhesives-is presented The method is based on the electrostatic bonding of a specially developed glass that has an ideal expansion match to the silicon solar cell Basically, the coverglass and cell are joined by a permanent chemical anodic bond formed by subjecting the cell and coverglass to voltage, temperature, and pressure while in intimate contact with each other Because the front surface of the solar cell forms one of the bonding interfaces, it is important to understand the significance of changes in the cell design or type Work performed in characterizing required cell parameters, eg coating type, texture, etc, and the effects of the bonding process on cell output are discussed >

Programmable bonding pad with sandwiched silicon oxide and silicon nitride layers

Abstract: The present invention is a bonding pad structure and method for making the same which can be connected at the metalization step to form passive or active devices in addition to forming a bonding pad. A P-doped region (24) is formed in an epitaxial layer (28) in the area of the bonding pad (30) at the perimeter of a chip. This P-doped region (24) allows the formation of a junction capacitance between it and the epitaxial layer (28). In addition, by adding an oxide layer (32) over the P-doped region (34) an oxide capacitor can be formed between the metal bonding pad (30) and the P-doped region (34) with the oxide (32) as the dielectric. The oxide layer (32) is a special sandwich of two layers, silicon dioxide (36) and silicon nitride (37). The sandwiched layers protects the components beneath the bonding pad (30). The P-doped region (34) can also be used as a resistance by providing metal connections to both ends. Finally, a vertical PNP transistor can be formed between the P-doped region (34), the epitaxial layer (28) and a P-doped substrate (26).

Production of composed liquid crystal display

Abstract: PURPOSE: To reduce a feeling of visual disorder by pressing and joining respective end faces of plural substrates against/to each other with a bonding agent consisting of polymeric materials and radiating laser beams to the projected bonding agent to etch it so that a level difference between the projection and the surface of the substrate is ≤5μm. CONSTITUTION: The bonding agent 6 consisting of polymeric materials is applied to the end faces of the circuit substrates to press the end faces of the substrates 1 against each other and preparatorily join them. In order to increase mechanical intensity, the rear face of the circuit substrate 1 may be joined with a base substrate. Laser beams 7 are radiated to the projected bonding agent 6 to etch the bonding agent 6 so that a level difference between the surface of the substrate 1 and the bonding agent 6 is ≤5μm. The circuit substrate 1 and an opposite substrate 3 are sealed with a bonding agent 4 for sealing them with a proper gap and liquid crystal 2 is injected to the gap. Consequently, a non- display area can be reduced and a feeling of visual disorder can be reduced. COPYRIGHT: (C)1989,JPO&Japio

Manufacture of sodium-sulfur battery

Abstract: PURPOSE:To obtain bonding substance excellent in corrosion resistance by using glass which has thermal expansion coefficient being smaller by 1-10X10 / deg.C than the thermal expansion coefficients of alpha-alumina and B''- alumina. CONSTITUTION:A solid electrolyte beta''-alumina to be 2 is arranged at the inner periphery of an alpha-alumina ring 1 for electric insulation, and glass powder is applied in slurry conditions, and is heated in the air so as to form a glass, with which those are joined together. In case that the thermal expansion coefficient of the glass is smaller than those of both aluminas, compressed stress remains at the surface of the glass after joining, and it improves the strength of the bonding substance. But, it if becomes too small, cracks occur inside the glass, which lowers the strength, so favorable strength and airtightness can be obtained within the range that the difference between both thermal expansion coefficients is 1-10X10 / deg.C. The glass, which has the above- mentioned thermal expansion coefficient, can be achieved by using glass in composition of 50-60mol% SiO2, 27-40mol% B2O3 and 10-13mol% Na2O from wettability, bonding property, etc., on limiting SiO2 to a maximum of 63mol% from corrosion resistance.

Sintered glass ceramic multilayer circuit board

Abstract: PURPOSE:To reduce an electric resistance and to enhance a bonding strength by using a wiring paste to which a metal to be oxidized more easily than a main component of the wiring paste without adding glass for bonding to the wiring paste has been added. CONSTITUTION:A metal which is oxidized more easily than a metal such as Au, Ag, Pt, Cu, Ni or the like as a main component of a wiring paste is added; while a metal to be oxidized easily by oxygen in a glass component during a sintering process or by oxygen in a sintering atmosphere is being oxidized, the metal is fused to a glass ceramic component; a bonding operation is executed by forming a diffusion layer. Thereby, a bonding interface without a void can be formed; main metals are bonded continuously in the central part of a conductor layer; the interface can be formed without damaging an electric resistivity of a conductor.

Bonding pad and manufacture thereof

Abstract: PURPOSE: To reduce the parasitic capacity of a bonding pad and to make it possible to improve the high-speed efficiency of a semiconductor device by a method wherein one or two or more of structures of an insulating film under a bonding metal and a conductive semiconductor substrate is/are partially hollowed out. CONSTITUTION: A bonding pad 3 is formed into a cross form conformed to the orientation property of a conductive semiconductor substrate 1 and a multitude of small holds are provided in the cross. Moreover, the regions of these small holes are respectively provided with each region 5 obtainable by etching away and hollowing out parts of an insulating film 2 and the substrate 1. In such a way, the contact area of the insulating film to contribute to the parasitic capacity of the substrate with the bonding pad can be reduced without lessening the diameter of the bonding pad and the contact property of a bonding metal 4 to the bonding pad can be improved by providing a multitude of the holes. Thereby, the unnecessary parasitic capacity of the bonding pad can be reduced without reducing the function of the bonding pad and a workability and the limit of speedup of a semiconductor device can be improved. COPYRIGHT: (C)1989,JPO&Japio

Silicon-on-insulator by wafer bonding and etch-back

Abstract: A novel silicon-on-insulator technique utilizing the bonding of oxidized silicon wafers has been investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces, which had been contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60-85 erg/cm/sup 2/ at room temperature to approximately=2200 erg/cm/sup 2/ at 1400 degrees C, which is in the same range as the cohesive energy of bulk quartz. The strength was essentially independent of the bond time. Bonds created during a 10 s annealing at 800 degrees C were strong enough to withstand both the thinning of the top wafer to the desired thickness and the subsequent device processing. Three distinct phases of the bonding process were observed. The electrical properties of the bond between the wafers were tested using MOS capacitors. The results were consistent with a negative charge density at the bond interface of approximately 10/sup 11/ cm/sup -2/. A double etch-back procedure was used to thin the device wafer to the desired thickness. The characteristics of the resulting film are described. CMOS devices made in a 0.3- mu m-thick layer had subthreshold slopes of 68 mV/decade (for both n- and p-channel MOS transistors). The effective carrier lifetime was >30 mu s in 300-nm-thick Si films, and the interface state density at the Si-film/buried oxide interface was >

Manufacture of semiconductor pressure sensor

Abstract: PURPOSE:To form a sensor which is superior in airtightness, chemical resistance, and mass-productivity by forming films of titanium, platinum, and gold on a glass pedestal 2 successively, sealing the other surface with a pressure sensor wafer electrostatically, and soldering a cut chip to a base. CONSTITUTION:The titanium film 12, platinum film 13, and gold film 14 are formed successively on one surface of the glass pedestal 2 and the pressure sensor wafer 16 where a diaphragm is formed is adhered to the other surface of the pedestal 2 by an anodic bonding (electrostatic sealing) method. This joined body is cut into chips, which are soldered to the base. Thus, titanium, etc., are used, so a metallic film does not deteriorate, the anodic bonding is possible, and no resin adhesive is used, so that the pressure sensor which is high in airtightness and strong in chemical resistance is obtained. Further, the solder adhesion to the base is employed, so the overheating time is much shorter than that of glass adhesion and the mass-productivity is improved.