Showing papers on "Anodic bonding published in 1996"

Surface activated bonding of silicon wafers at room temperature

Abstract: A method to bond silicon wafers directly at room temperature was developed. In this method, surfaces of two silicon samples are activated by argon atom beam etching and brought into contact in a vacuum. By the infrared microscope and KOH etching method, no void at the bonded interface was detected in all the specimens tested. In the tensile test, fracture occurred not at the interface but mainly in the bulk of silicon. From these results, it is concluded that the method realizes strong and tight bonding at room temperature and is promising to assemble small parts made by the silicon wafer process.

Method for manufacturing a semiconductor acceleration sensor device

Abstract: On a silicon wafer there is formed a movable gate MOS transistor (sensing element: functional element). A bonding frame consisting of a silicon thin film is patterned around an element formation region on the surface of the silicon wafer. On a cap forming silicon wafer there is projectively provided a leg portion on the bottom surface of which a bonding layer consisting of a gold film is formed. The cap forming silicon wafer is disposed on the silicon wafer, whereupon heating with respect thereto is performed at a temperature equal to higher than a gold/silicon eutectic temperature to thereby make bondage between the bonding frame of the silicon wafer and the bonding layer of the cap forming silicon wafer. Thereafter, the both wafers are diced in chip units.

Diffuser-element design investigation for valve-less pumps

Abstract: The flow-directing properties of several micromachined diffuser elements with different lengths and opening angles for valve-less micropumps have been investigated. The experimental results are compared with analytical results. The diffuser elements are fabricated in silicon and glass using isotropic and anisotropic wet etching and anodic bonding. The lengths of the diffusers are from 1.45 to 3.95 mm and the half-elliptic neck cross sections are about 30 μm × 100 μm.

Fabrication of single-crystal silicon structures using sacrificial-layer wafer bonding

Abstract: A thin micromechanical device is fabricated in a way that is mechanically compatible with wafer handling for conventional-thickness wafers. A removable bonding layer bonds a fabrication wafer to a substantially conventional-thickness handle wafer to form a bonded wafer pair. The micromechanical device is formed in the fabrication wafer by subjecting the bonded wafer pair to processing including wafer handling for conventional-thickness wafers. The micromechanical device is formed to include part of the fabrication wafer. Finally, the bonding layer underlying the micromechanical device is removed to release the micromechanical device from the handle wafer.

Physics and chemistry of silicon wafer bonding investigated by infrared absorption spectroscopy

Abstract: Silicon wafer bonding is achieved by joining two particle‐free silicon wafers and annealing to elevated temperatures (∼1100 °C). We have used multiple internal transmission infrared absorption spectroscopy to probe the interface between the wafers upon initial joining and also during subsequent annealing steps. For atomically flat hydrophobic wafers (H passivated), we observe a pronounced shift in the Si–H stretching frequency due to the physical interaction (van der Waals attraction) that occurs when the surfaces come into intimate contact. The hydrogen eventually disappears at high temperatures (1000 °C) and Si–Si bonds are formed between the two surfaces. For hydrophilic wafers (oxide passivated), we initially observe three to five monolayers of water at the interface (providing the initial attraction through H bonding), as well as the presence of hydroxyl groups that terminate the oxide at low temperature. Upon moderate heating (<400 °C), the water trapped at the interface dissociates and leads to the formation of additional oxide. Between 400 and 800 °C, the hydroxyl groups disappear, resulting in a corresponding increase in oxide and the formation of Si–O–Si bridging linkages across the two surfaces.

Sealed cavity arrangement method

Abstract: This invention relates to a method for making sealed cavities on silicon wafer surfaces by anodic bonding and with electrically insulated conductors through the sealing areas to connect functional devices inside the cavities to electrical terminals outside said cavities. Said conductors are provided by the use of doped buried crossings in a single crystal silicon substrate, thereby also allowing different kinds of integrated silicon devices, e.g. sensors to be made. Further, the invention relates to a device made by the novel method.

A Model of Low‐Temperature Wafer Bonding And Its Applications

Abstract: Si‒OH groups can polymerize to form strong covalent Si‒O‒Si bonds at low temperatures. Based on this behavior a model for hydrophilic Si wafer bonding is suggested which allows significant increase of bonding strength by low‐temperature annealing. A possible extension of this model to materials other than Si is discussed. Methods to prevent generation of interface bubbles during the low‐temperature annealing are presented. The low‐temperature bonding approach has been employed in layer transfer applications such as an ultrathin silicon‐on‐insulator layers by an implanted carbon etch stop, single‐crystal Si layer on quartz, glass, or sapphire. Analysis of thermal peeling stresses in bonded pairs of dissimilar materials led to the development of bonding and heating‐cooling schedules as well as a low vacuum bonding method to avoid peeling during annealing and subsequent thinning (etching).

Capacitive pressure sensor

Abstract: PURPOSE: To provide a capacitive pressure sensor designed to improve the linearity of output characteristics while the pressure sensitivity is set high in a required state. CONSTITUTION: A silicon substrate 10 with a diaphragm 13 and a flat glass substrate 11 are united by anodic bonding. A pressure introduction path 17 is formed to penetrate the glass substrate up and down, making it possible to supply a measuring pressure P to a pressure chamber 14. A pressure leak groove 18 is formed at a predetermined position of a bonding face of the silicon substrate at the side bonded to the glass substrate. Accordingly, a part of the measuring pressure is let to leak outside through the pressure leak groove. The leaking amount is determined by a correlation of a cross sectional area S2 of the leak groove and an area S1 of the pressure introduction path. A ratio of the leaking amount to the supplying amount of gas decreases in accordance with an increase of the pressure. Since the ratio of the leaking amount is non-linear, the non-linearity of the deflecting amount of the diaphragm to the pressure is offset, thus widening an area of the linearity.

Room-temperature CW operation of InGaAsP lasers on Si fabricated by wafer bonding

Abstract: 1.3-/spl mu/m InGaAsP-InP lasers have been successfully fabricated on Si substrates by wafer bonding with heat treatment at 400/spl deg/C. A pressure of 4 kg/cm/sup 2/ has been applied on the wafers before the heat treatment and this pressure application has enabled us to achieve bonding strength required for the device fabrication even when the bonding temperature is as low as 400/spl deg/C. Room-temperature continuous-wave operation with threshold current of 49 mA has been achieved for 7-/spl mu/m-wide mesa lasers.

Fabrication of SOI wafers with buried cavities using silicon fusion bonding and electrochemical etchback

Abstract: This paper describes a new technique for batch fabrication of silicon-on-insulator (SOI) wafers for microelectromechanical systems (MEMS) applications by silicon wafer bonding techniques. The process permits the inclusion of buried cavities in the SOI wafers, providing a useful tool for sensor and actuator fabrication using the resulting wafers. A low-cost electrochemical etchback step is used to define accurately the thickness of the remaining single-crystal material even though the two wafers are bonded with an intermediate insulating oxide layer. The results presented include guidelines for backside contact definition which maximize the useful silicon area as a function of doping level. The final single-crystal silicon thickness is uniform to within 0.05 μm (standard deviation) and does not require any costly high-accuracy polishing steps.

Smoothing of ultrasonically drilled holes in borosilicate glass by wet chemical etching

Abstract: Besides silicon various types of glass play an important role in microsystem technology. One requirement of the glasses is that they have to be microstructurable. In many applications for microsensors and microstructures the glass must be suitable for anodic bonding. Usually borosilicate glass (e.g. Corning Pyrex code 7740 glass) is used, which has a thermal expansion coefficient that is almost equal to the thermal expansion coefficient of silicon and which has the necessary electrical conductivity at the temperature at which the bonding process occurs. For many applications, e.g., microfluidic systems, it is necessary to have fluids flown through ultrasonically drilled holes in the Pyrex glass to the silicon chip. The main objective of the investigation was to obtain smooth walls of ultrasonically drilled holes because every contamination influences the performance of the microsystem. In this paper the ultrasonic drilling method is compared with two other procedures for machining holes (sand blasting and laser machining). Other ways of structuring glass have been presented previously. A process was developed to smooth the walls of the drilled holes with different concentrations of hydrofluoric acid.

Method of anodic wafer bonding

Abstract: A process is provided for protecting, containing, and/or completing fragile microelectronic and microelectromechanical (MEM) structures on a low conductivity substrate during anodic wafer bonding of a covering wafer. The wafer includes raised areas that contact the substrate at selected bonding regions to support the wafer as a covering structure over the substrate. The covering wafer includes additional raised areas, such as pillars or posts, that contact selected electric circuit lines on the substrate to form temporary shorts through the wafer. During anodic bonding of the wafer to the substrate, the temporary shorts maintain the connected circuit lines and microstructures at nearly the same electric potential to prevent unwanted arcing and electrostatic forces that could damage the fragile structures. The pillars or posts can be formed at the same time as the raised bonding areas, but on unwanted and otherwise unused portions of the covering wafer. Anodic bonding produces only weak bonds between the wafer posts and the metallic conductor material of the circuit lines. After anodic bonding, the unwanted portions of the covering wafer can be removed to leave covering structures over the selected microstructures. Because of the weak bonds, removal of the unwanted portions of the wafer also removes the posts and eliminates the temporary shorts, with no additional processing needed to electrically separate the circuit lines on the substrate.

Fabrication of a silicon-Pyrex-silicon stack by a.c. anodic bonding

Abstract: This paper reports a new mounting technique for bonding silicon-Pyrex-silicon based on anodic bonding and alternating current (a.c.) excitation. The bond is mechanically stable and strong enough to withstand a shear force of at least 1 MPa, or further reactive ion and wet chemical etching processes. The technique has been optimized to be independent of various modifications of the stack dimensions or bonding parameters (e.g., temperature, voltage, quality of the contact).

Gas development at the interface of directly bonded silicon wafers: investigation on silicon-based pressure sensors

Abstract: Hydrophobic and hydrophilic silicon direct bonding (SDB) under vacuum conditions are compared with respect to the capability to form hermetically sealed cavities with minimal enclosed residual gas pressure. The quality of the enclosed vacuum inside the cavities of pressure-sensor test structures is monitored for different cavity layouts and annealing processes. The observed pressure increase during annealing is found to be strongly dependent on annealing temperature, subsequent storage time and on the bonded area surrounding each cavity. Trapped gaseous reaction products originating at the bonding interface are responsible for this effect. There is a significant difference in annealing-related gas evolution for hydrophobic and hydrophilic bonding surfaces, which can be explained by the existing theories of the bonding mechanism. Hydrophobic bonding leads to about 50% lower residual gas pressures compared with hydrophilic bonding. For hydrophilically bonded wafers a slow saturation of the gas pressure after annealing is observed.

An improved valve-less pump fabricated using deep reactive ion etching

Abstract: We present the first valve-less diffuser pump fabricated using the latest technology in deep reactive ion etching (DRIE). The pump is fabricated in a simple micromachining process in a double side polished silicon wafer anodically bonded to a glass wafer. Pump chambers and diffuser elements are etched in the silicon wafer using DRIE while inlet and outlet holes are etched using an anisotropic KOH-etch. The DRIE etch resulted in rectangular diffuser cross-sections. We present results on pumps with different diffuser dimensions in terms of diffuser neck width, length and angle. We reached a maximum pump pressure of 7.6 m H/sub 2/O (74 kPa) and maximum pump flow of 2.3 ml/min for water.

Silicon-silicon anodic-bonding with intermediate glass layers using spin-on glasses

Abstract: This paper presents for the first time the preparation of glass layers, suitable for the anodic bonding of two silicon substrates using a spin-on glass. In this process a liquid sol solution is used within a spin coating process. The solution is a mixture based on silica sol, organic silicon containing compounds, like TEOS (Tetraethylorthosilicate), and a sodium salt all dissolved in ethanol. After a careful thermal treatment, silica films containing up to 5% wt. Na/sub 2/O (sodium oxide) can be obtained with a thickness in the range from 600 nm to 1000 nm in one deposition step. The spin-on glass films are very smooth. Anodic bonding of two silicon substrates is possible with all films either prepared at temperatures of 420/spl deg/C, 540/spl deg/C or even higher.

Solid-state reaction bonding of silicon carbide (HIPSiC) below 1000°C

Abstract: A solid-state method of joining Si-free hot isostatically pressed SiC (HIP SiC) at relatively low temperatures is described. The bonding method involved prereacting of HIP SiC specimens with Cr at 1000°C to produce the required thermodynamically stable ternary phase (τ, Cr5Si3C) and then diffusion bonding of the coated specimens employing Ni foil as an intermediate layer. The diffusion bonding of the prereacted specimens was carried out in a locally heated diffusion bonding equipment in a temperature range 700–1000°C. The quality of the joint was assessed by microstructural characterisation. The coatings obtained on the HIP SiC specimens acted as a diffusion barrier and avoided excessive reaction between Ni and SiC. Optimum bonding conditions were 940°C and 3 h. Scanning electron microscopy (SEM)/energy-dispersive X-ray microanalysis (EDX) and metallographic analysis showed good metallurgical compatibility and the absence of discontinuities and micropores at the interfaces in the bonded assembly. The proposed bonding scheme is superior to bonding SiC using Ni or Ni Cr foils alone. The excellent control of the reaction zone width and morphology also opens the prospect of joining SiC to Ni base alloys.

Bonding pad for a semiconductor chip

Abstract: Disclosed is a bonding pad for a semiconductor chip which prevents damage during a bonding process. In a semiconductor chip having conductive regions interconnected by a metal pattern, a metal region is disposed over the metal pattern. The metal region forms a bonding pad area over the conductive regions. In addition, the metal region is in direct contact with the metal pattern for substantially the whole bonding pad area. With this arrangement, the metal region absorbs mechanical stress induced when a bonding wire is bonded to the metal region during a bonding process. The metal region is sufficiently thick so as not to be perforated during the bonding process and the metal pattern is, therefore, not damaged.

Cleaning and polishing as key steps for Smart-cut(R) SOI process

Abstract: Silicon on insulator technologies appear to be suitable for low power and low voltage electronics. SIMOX wafers have been considered as the best candidates to realize ULSI devices. An alternative route has been proposed by M. Bruel (1995-96) referred to as the Smart-cut process. This new process is versatile enough to fabricate SOI structures (Unibond wafers) with tuned silicon and oxide layer thicknesses. Good thickness homogeneity, low defect density, high surface quality and good electrical properties are now available in these SOI wafers. The authors show that most of these parameters depend, to some degree, on the cleaning step before wafer bonding or on the final chemical mechanical polishing process. As an example, surface roughness and defect densities are investigated by comparison with SIMOX wafer results.

Ultrasonic bonding method and ultrasonic bonding apparatus

Abstract: In a case of ultrasonic bonding of a bonding wire to a metal pad provided on a semiconductor substrate, the vibration amplitude of a tip end of the bonding tool is set to be smaller than the film thickness of the metal pad, and the vibration frequency of the bonding tool is set to be higher than 70 kHz. According physical damage, such as cracks produced in a portion beneath the metal pad, can be prevented.

Micromachined diffuser/nozzle elements for valve-less pumps

Abstract: We present an investigation of the flow directing properties of several micromachined diffuser elements with different lengths and opening angles for valve-less micropumps. The lengths of the diffusers are from 1.45 to 3.95 mm and the half-elliptic cross-sections about 30/spl times/100 /spl mu/m. Analytical results are compared to experimental results on individual diffuser chips and diffusers in a pump chip. The diffuser elements were fabricated in silicon and glass using isotropic and anisotropic etching and anodic bonding.

A fiber-optic silicon pressure sensor for ultra-thin catheters

Abstract: We have developed a new type of fiber-optic pressure microsensor (sensing-element size: 350 μm × 350 μm × 350 μm) suitable for medical instruments such as catheters and endoscopes. The sensing element consists of a diaphragm structure, glass plate and alignment structure. For the transmitting source and signal light, a multimode optical fiber 50/125 μm (core/clad) in diameter has been used. The sensors have been fabricated using micromachining, for example, anisotropic etching and anodic bonding. Pressure measurement is based on modulation of the intensity of optical reflection by deflection of the diaphragm. Pressure measurements of the sensor with sufficient sensitivity (0.19 μW MPa −1 on the average) and accuracy have been obtained.

Mechanism of Enlargement of Intimately Contacted Area in Anodic Bonding of Kovar Alloy to Borosilicate Glass

Abstract: The effects of the bonding temperature and voltage on the rate of the enlargement of intimately contacted area in the anodic bonding of the Kovar alloy to borosilicate glass have been studied systematically in order to obtain better understanding of the rate controlling factor of the process. It was suggested that the attainment of intimate contact was controlled by two factors having different activation energies depending on the bonding temperature. At bonding temperatures higher than 669-687 K (depending on the bonding voltage), the estimated activation energy was close to that of the viscous flow of the glass. At lower bonding temperatures, the estimated activation energy was close to that of the conductivity of the glass. A mechanism of the enlargement of intimately contacted area during the anodic bonding is proposed to explain these results.

The influence of wafer dimensions on the contact wave velocity in silicon wafer bonding

Abstract: The contact wave velocity in silicon wafer bonding is experimentally found to decrease with wafer thickness and to be only weakly dependent on wafer diameter. Wafers of different thicknesses ranging from 270 to 5000 μm, were dipped in HF:H2O before bonding to give the surfaces hydrophobic properties. A model based on energy conservation can explain the main characteristics of the experimental results. The contact wave velocity is determined by the amount of energy available as kinetic energy for the entrapped gas in the gap between the wafers. By increasing wafer thickness, the elastic energy stored in the material is increased, and the contact wave velocity is decreased.

Curvature changing or flattening of anodically bonded silicon and borosilicate glass

Abstract: A method has been developed to change or to remove stress in anodically bonded silicon and glass compounds (Pyrex or Tempax). The technology is based on the structural relaxation of the glass at temperatures at which no viscous flow is to be seen. Due to the structural relaxation, a shrinkage of the glass occurs at sufficiently high temperatures and leads to a bend change of the bonded wafers. As a result, at room temperature or at the working temperature stress-free compounds as well as those with lower and even with opposite stress and curvature can be produced. The structural relaxation of the glass has been studied by investigating the shrinkage of glass rods during isothermal annealing. The applicability to the curvature change of anodically bonded silicon and Tempax has been proved. Finally, the influence of the developed method on the decomposition and on the thermal expansion coefficient of the glass has been studied.

Method of manufacturing image display apparatus using bonding agents

Abstract: A method of manufacturing an image display apparatus, which has a first substrate on which an electron emission element is arranged, a second substrate on which a phosphor that forms an image upon irradiation of an electron emitted by the electron emission element is arranged, and an enclosure which is bonded to the first and second substrates to hold a gap between the first and second substrates, has the steps of applying a bonding agent to bonding portions between the first and second substrates, and the enclosure, heating to a temperature equal to or more than the softening temperature of the bonding agent, detecting the solidification state of the bonding agent, performing position alignment between the first and second substrates during the interval after the bonding agent softens until the bonding agent solidifies, bonding the first and second substrates via the enclosure by compressing the first substrate and/or the second substrate, and releasing the compression force to the first substrate and/or the second substrate.

Investigation on direct bonding of III-V semiconductor wafers with lattice mismatch and orientation mismatch

Abstract: The direct bonding of various III–V wafers with mismatches in terms of lattice constants and surface orientations was systematically investigated for an In–Ga–As–P system. Many wafer combinations were bonded with sufficient mechanical strength, despite those mismatches. The bonding interface of (001) GaP and (110) InP was observed by transmission electron microscopy and found to be bonded at the atomic level without any defects occurring. The electrical property of the bonding interface was examined for several bonded structures of GaAs and InP. The results support a novel concept ‘‘free‐orientation integration,’’ which should be achieved by direct bonding.

Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding

Abstract: Reports here the first results of using plasma enhanced CVD TEOS (Si(C/sub 2/H/sub 5/O)/sub 4/) oxide (PETEOS) and associated CMP (Chemical Mechanical Polishing) technology to form a flat layer on the surface of a processed VLSI bulk Si wafer for direct bonding. The undoped PETEOS oxide has also been used as a bonding layer for substrates onto which the IC layer is to be transfered and whose surfaces are not favorable for bonding.