Showing papers on "Anodic bonding published in 2008"

Wafer level packaging of MEMS

Abstract: Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

Highly efficient vertical outgassing channels for low-temperature InP-to-silicon direct wafer bonding on the silicon-on-insulator substrate

Abstract: The authors report a highly efficient design for low-temperature, void-free InP-to-silicon direct wafer bonding on a silicon-on-insulator (SOI) substrate. By etching an array of small through holes in the top silicon layer, the generated gas by-products (H2O, H2) from bonding polymerization reactions and thus gaseous hydrocarbon can be absorbed and diffuse in the buried oxide layer, resulting in up to five orders of magnitude interfacial void density reduction (from >50 000 to ≤3 cm−2). The required annealing time is reduced to less than 30 min, a ∼100X improvement compared to the previous outgassing design as well. Comprehensive studies in associated processing details, bonding surface energy, universality, and stability are also presented. Successful 50, 75, and 100 mm InP expitaxial layer transfer to the SOI substrate is also demonstrated, which indicates a total elimination of outgassing issues regardless of the wafer bonding dimension. Several incidental advantages leading to a flexible device design...

Bonding Technique Using Micro-Scaled Silver-Oxide Particles for In-Situ Formation of Silver Nanoparticles

Abstract: We investigated a new bonding technique utilizing micro-scaled silver-oxide (Ag 2 O) particles. The results of our investigations revealed that bonding between electrodes using for semiconductor modules can be accomplished by adding myristyl alcohol to silver-oxide particles, followed by heating the mixture in air at 300°C under a pressure of 2.5 MPa. Since this bonding technique produces silver particles with a size of a few nanometers when the silver oxide is reduced by the presence of the alcohol, low-temperature sintering and bonding can be achieved.

Study of Bonding Technology Using Silver Nanoparticles

Abstract: We investigated a new bonding technique utilizing nano-scaled particles for use in high-temperature environments. The results of our investigations revealed that the method could be used to form bonds by simultaneously applying heat and pressure. Moreover, compared to a conventional Pb–5Sn-solder bond, a nanoparticle-based bond suffered no degradation in bonding strength over an elevated-temperature holding period of 1000 h at 250 °C, and its discharge characteristics were improved (i.e., increased) threefold. It is possible to extend this bonding technique to mounting components in devices that operate in high-temperature environments, e.g., it can be used to mount components such as silicon carbide (SiC) devices, which are expected to be applied in environments with temperatures exceeding 250 °C.

Solventless Adhesive Bonding Using Reactive Polymer Coatings

Abstract: A novel solventless adhesive bonding (SAB) process is reported, which is applicable to a wide range of materials including, but not limited to, poly(dimethylsiloxane) (PDMS). The bonding is achieved through reactions between two complementary polymer coatings, poly(4-aminomethyl-p-xylylene-co-p-xylylene) and poly(4-formyl-p-xylylene-co-p-xylylene), which are prepared by chemical vapor deposition (CVD) polymerization of the corresponding [2.2]paracyclophanes and can be deposited on complementary microfluidic units to be bonded. These CVD-based polymer films form well-adherent coatings on a range of different substrate materials including polymers, glass, silicon, metals, or paper and can be stored for extended periods prior to bonding without losing their bonding capability. Tensile stress data are measured on PDMS with various substrates and compared favorably to current methods such as oxygen plasma and UV/ozone. Sum frequency generation (SFG) has been used to probe the presence of amine and aldehyde gro...

A Compact Angular Rate Sensor System Using a Fully Decoupled Silicon-on-Glass MEMS Gyroscope

Abstract: This paper presents the development of a compact single-axis angular rate sensor system employing a 100- mum-thick single-crystal silicon microelectromechanical systems gyroscope with an improved decoupling arrangement between the drive and sense modes. The improved decoupling arrangement of the gyroscope enhances the robustness of sensing frame against drive-mode oscillations and therefore minimizes mechanical crosstalk between the drive and sense modes, yielding a small bias instability. The gyroscope core element is fabricated by through-etching a 100-mum -thick silicon substrate which is anodically bonded to a recessed glass handling substrate. A patterned metal layer is included at the bottom of the silicon substrate, both as an etch-stop layer and a heat sink to prevent heating- and notching-based structural deformations encountered in deep dry etching in the silicon-on-glass process. The fabricated-gyroscope core element has capacitive actuation/sensing gaps of about 5 mum yielding an aspect ratio close to 20, providing a large differential sense capacitance of 18.2 pF in a relatively small footprint of 4.6 mm times 4.2 mm. Excitation and sensing electronics of the gyroscope are constructed using off-the-shelf integrated circuits and fit in a compact printed circuit board of size 54 mm times 24 mm. The complete angular rate sensor system is characterized in a vacuum ambient at a pressure of 5 mtorr and demonstrates a turn-on bias of less than 0.1 deg/s, bias instability of 14.3 deg/h, angle random walk better than 0.115 deg/radic(h), and a scale-factor nonlinearity of plusmn0.6% in full-scale range of plusmn50 deg/s. [2007-0158].

Hydrophilic low-temperature direct wafer bonding

Abstract: The sealing mechanism of silicon bonding interfaces is reported as a function of annealing temperature. Details of the structural and chemical interface evolution are obtained for hydrophilic silicon/silicon and silicon/silicon dioxide wafer bonding, using x-ray reflectivity and infrared spectroscopy. A two-step mechanism is demonstrated: first a partial sealing of the interface driven by cross-wafer silanol bond condensation and second a water evacuation via oxide formation at the silicon oxide interface.

Cylindrical bonding structure and method of manufacture

Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder.

High-temperature spin-on temporary bonding compositions

Abstract: New compositions and methods of using those compositions as bonding compositions are provided The compositions are preferably thermoplastic and comprise imides, amideimides, and/or amideimide-siloxanes (either in polymeric or oligomeric form) dispersed or dissolved in a solvent system, and can be used to bond an active wafer to a carrier wafer or substrate to assist in protecting the active wafer and its active sites during subsequent processing and handling The compositions form bonding layers that are chemically and thermally resistant, but that can also be softened to allow the wafers to slide apart at the appropriate stage in the fabrication process

Cmos integrated circuits with bonded layers containing functional electronic devices

Abstract: A complementary metal oxide semiconductor (CMOS) circuit having integrated functional devices such as nanowires, carbon nanotubes, magnetic memory cells, phase change memory cells, ferroelectric memory cells or the like. The functional devices are integrated with the CMOS circuit. The functional devices are bonded (e.g. by direct bonding, anodic bonding, or diffusion bonding) to a top surface of the CMOS circuit. The functional devices are fabricated and processed on a carrier wafer, and an attachment layer (e.g. SiO2) is deposited over the functional devices. Then, the CMOS circuit and attachment layer are bonded. The carrier wafer is removed (e.g. by etching). The functional devices remain attached to the CMOS circuit via the attachment layer. Apertures are etched through the attachment layer to provide a path for electrical connections between the CMOS circuit and the functional devices.

Bonding apparatus and bonding method

Abstract: A bonding apparatus ( 10 ) that bonds an electrode of a semiconductor die ( 12 ) and an electrode of a circuit board ( 19 ) using a metal nano paste includes a bump formation mechanism ( 20 ) that forms bump by injecting microdroplets of a metal nano paste on each electrode, a primary bonding mechanism ( 50 ) that carries out primary bonding to the electrodes in a non-conductive state by pressing the bump of the semiconductor die ( 12 ) against the bump of the circuit board ( 19 ), and a secondary bonding mechanism ( 80 ) that includes a pressurizing unit that pressurizes the primary bonded bump in bonding direction, and that carries out secondary bonding so that the electrodes become conductive by heating the bump up to a temperature higher than a binder removal temperature of the metal nano paste and a dispersant removal temperature of the metal nano paste, removing the binder and the dispersant, and pressurizing and sintering the metal nanoparticles in the bump. With this, it is possible to efficiently bond the electrodes with a simple and easy way while reducing a bonding load.

Gold-indium Transient Liquid Phase (TLP) wafer bonding for MEMS vacuum packaging

Abstract: This paper reports the first wafer-level vacuum packages created with gold-indium transient liquid phase (TLP) wafer bonding. The packages were bonded at 200degC for 1 hour under a vacuum environment in a commercially available wafer bonder. After bonding, the integrated getters were activated for 1 hour resulting in internal pressures as low as 200 mTorr. The pressures have been stable for over 6 months as measured by integrated Pirani gauges. Although no leak rate trend has been observed, the worst case leak rate that fits within the error of the pressure measurement is 16 mTorr/year (1ldr10-16 atm.cc.s-1).

Calcium-Assisted Glass-to-Glass Bonding for Fabrication of Glass Microfluidic Devices

Abstract: Glass is a desired material for many microfluidics applications. It is chemically resistant and has desirable characteristics for capillary electrophoresis. The process to make a glass chip, however, is lengthy and inconvenient, with the most difficult step often being the bonding of two planar glass substrates. Here we describe a new glass bonding technique, which requires only washing of the glass surfaces with a calcium solution and 1−2 h of bonding at 115 °C. We found calcium uniquely allows for this simple and efficient low-temperature bonding to occur, and none of the other cations we tried (e.g., Na+, Mg2+, Mn3+) resulted in satisfactory bonding. We determined this bond is able to withstand high applied field strengths of at least up to 4 kV·cm−1. When intense pressure was applied to a fluid inlet, a circular portion of the coverslip beneath the well exploded outward but very little of the glass−glass interface debonded. In combination with the directed hydrofluoric acid etching of a glass substrat...

Wafer bonding activated by ion implantation

Abstract: A method for wafer bonding two substrates activated by ion implantation is disclosed. An in situ ion bonding chamber allows ion activation and bonding to occur within an existing process tool utilized in a manufacturing process line. Ion activation of at least one of the substrates is performed at low implant energies to ensure that the wafer material below the thin surface layers remains unaffected by the ion activation.

Thermally activated solvent bonding of polymers

Abstract: We present a thermally activated solvent bonding technique for the formation of embedded microstructures in polymer. It is based on the temperature dependent solubility of polymer in a liquid that is not a solvent at room temperature. With thermal activation, the liquid is transformed into a solvent of the polymer, creating a bonding capability through segmental or chain interdiffusion at the bonding interface. The technique has advantages over the more commonly used thermal bonding due to its much lower operation temperature (30°C lower than the material’s T g), lower load, as well as shorter time. Lap shear test indicated bonding shear strength of up to 2.9 MPa. Leak test based on the bubble emission technique showed that the bonded microfluidic device can withstand at least six bars (87 psi) of internal pressure (gauge) in the microchannel. This technique can be applied to other systems of polymer and solvent.

Glass-blown spherical microcells for chip-scale atomic devices

Abstract: This paper demonstrates spherical vapor cells intended to be used in chip-scale atomic devices. A micro glass blowing process is introduced, in which multiple glass spheres are simultaneously shaped on the top of a silicon wafer and subsequently filled with rubidium. In the presented fabrication process, an array of cylindrical cavities is first etched in silicon. Next, a thin glass wafer is anodically bonded to the silicon wafer. The bonded wafers are then placed inside a furnace set to 850 ° C. At this elevated temperature, the viscosity of the glass is decreased and the heated trapped gas in the cavities expands, thus causing the glass to be blown into spherical cells. Microscopic alkali vapor cells are achieved by evaporation of Rb 87 through a small glass nozzle into the cell cavities. The cells are then sealed by anodic bonding. The fabricated cells are characterized and the presence of rubidium vapor inside the cells is verified by observing an absorption spectrum.

Implementation of silicon-on-glass MEMS devices with embedded through-wafer silicon vias using the glass reflow process for wafer-level packaging and 3D chip integration

Abstract: This study presents a novel system architecture to implement silicon-on-glass (SOG) MEMS devices on Si–glass compound substrate with embedded silicon vias. Thus, the 3D integration of MEMS devices can be accomplished by means of through-wafer silicon vias. The silicon vias connecting to the pads of devices are embedded inside the Pyrex glass. Parasitic capacitance for both vias and microstructures is decreased and mismatch of coefficient of thermal expansion (CTE) is reduced. In applications, the glass reflow process together with the SOG micromachining processes were employed to implement the presented concept. Successful driving of the resonator through the silicon vias is demonstrated. The wafer-level hermetic packaging can be further achieved by anodic bonding of a Pyrex7740 wafer. Hermeticity of the packaged device performed by helium leak test satisfied MIL-STD-883E. The packaged SOG device is SMT (surface mount technology) compatible and ready for 3D microsystem integration.

Microfluidic on chip viscometers.

Abstract: We present the design and the process of fabrication of micromachined capillary on chip rheometers which have performed wall shear stress and shear rate measurements on silicon oil and ethanol-based nanofluids The originality of these devices comes from the fact that local pressure drop measurements are performed inside the microchannels Thus, the advantage over existing microviscometers is that they can be used with the fluid under test alone; no reference fluid nor posttreatment of the data are needed Each on chip viscometer consists of anodically bonded silicon-Pyrex derivative microchannels equipped with local probes The anodic bonding allows to reach relatively high pressure levels (up to ≈10bars) in the channels, and a broad range of shear stress and shear rate values is attainable Dielectrophoretic and electrorheological effects can be highlighted by employing alternate microstripe electrodes patterned onto the inner side of the Pyrex wall

Temporary Bonding and DeBonding Enabling TSV Formation and 3D Integration for Ultra-thin Wafers

Abstract: As the microelectronics industry promotes emerging and future applications, new and improved methods will be necessary to meet the manufacturing challenges associated with new products and processes. Emerging products and applications such as heterogeneous integrated chips (3D, TSV-through silicon via), radio-frequency identification tags, ever denser memory devices along with the advent of new advanced packaging technologies for a variety of products ranging from logic to memory to image sensors (CIS) require increasingly thinner substrates. While thin (<100 mum) silicon wafers exhibit increased flexibility, which in some cases is actually desired, such wafers also exhibit increased instability and fragility. The increased degree of fragility becomes even more pronounced in compound semiconductor wafers because of the mechanical properties of the constituent materials. The lack of mechanical stability and the increased fragility present a major challenge to maintaining high yield levels in volume manufacturing environments. A reliable support and handling solution is needed to overcome the above-mentioned challenges while maintaining yield levels compatible with low-cost, high-yield manufacturing processes. The solution of choice must enable safe, reliable handling of the substrates through back-thinning and backside processing while being compatible with existing (already installed) equipment lines and manufacturing processes. The most promising and most widely investigated handling solution for UltraThinreg wafers is the use of temporary bonding and debonding techniques utilizing a rigid carrier wafer to provide sufficient mechanical support. Once the product wafer is temporarily bonded to the carrier wafer, it is ready for backside processing including back-thinning, through-silicon via formation, etc. The product wafers can either be pre-processed wafers with CMOS devices as well as e.g. substrates with high-topographies like solder-balls. After completion of the backside processing steps, the product wafer can be released from the carrier wafer and proceed to final packaging processes. This paper will discuss and describe the temporary bonding process step technology, including spin/spray coating process to apply the high performance BrewerScience intermediate adhesive and the subsequent bonding step in detail. The EVG850TB (temporary bonding) equipment and the related process modules to cover this process are explained in addition. Furthermore, backside-processes (like e.g. thinning, backside metallization,.etc) which are typically applied after bonding to form e.g. TSV (through silicon via's) and the corresponding process performance are described. Once the original bonded waferstack went successfully through the backside process steps, debonding will be performed. DeBonding, in this case means, that first the thin wafer is getting debonded via thermally activated slide lift-off approach from the carrier wafer, cleaned in a single wafer cleaning chamber in order to remove the remaining adhesive residuals and than transferred to the dedicated output format. Output formats typically are either filmframe carriers, dedicated wafer cassettes, coin stack packing canisters or e.g. single wafer carriers. The carrier wafer is also getting cleaned and can then be reused again immediately for another bond-process. The EVG850DB (debonding bonding) equipment and the related process modules to cover this process are explained in detail. The paper will conclude with a discussion and comparison of silicon and glass carriers used for temporary bonding with respect to process integration and CoO.

Wafer-level plasma activated bonding: new technology for MEMS fabrication

Abstract: Manufacturing and integration of MEMS devices by wafer bonding often lead to problems generated by thermal properties of materials. These include alignment shifts, substrate warping and thin film stress. By limiting the thermal processing temperatures, thermal expansion differences between materials can be minimized in order to achieve stress-free, aligned substrates without warpage. Achieving wafer level bonding at low temperature employs a little magic and requires new technology development. The cornerstone of low temperature bonding is plasma activation. The plasma is chosen to compliment existing interface conditions and can result in conductive or insulating interfaces. A wide range of materials including semiconductors, glasses, quartz and even plastics respond favorably to plasma activated bonding. The annealing temperatures required to create permanent bonds are typically ranging from room temperature to 400°C for process times ranging from 15–30 min and up to 2–3 h. This new technique enables integration of various materials combinations coming from different production lines.

Glass for anodic bonding

Abstract: The present invention provides a glass for anodic bonding having a low thermal expansion coefficient and capable of being subjected to laser beam micromachining. The present invention is a glass for anodic bonding having a base glass composition containing 1 to 6 mol % of Li 2 O+Na 2 O+K 2 O and having an average linear expansion coefficient of 32×10 −7 K −1 to 39×10 −7 K −1 in a temperature range of room temperature to 450° C. This glass further contains 0.01 to 5 mol % of a metal oxide as a colorant relative to the base glass composition, and has an absorption coefficient of 0.5 to 50 cm −1 at a particular wavelength within 535 nm or less.

Copper direct bonding for 3D integration

Abstract: In 3D integration circuits, metal bonding is a key stage for stacking wafers. In this contribution, the direct Cu/Cu bonding at atmospheric pressure is investigated. At room temperature, a 2.8 J/m2 bonding toughness is achieved without copper oxide at the interface. The vertical current of this bonding and the possibility to grind the top silicon down to 10 ?m have been demonstrated.

New approach of fabrication and dispensing of micromachined cesium vapor cell

Abstract: We describe the fabrication of wafer-scale alkali vapor cells based on silicon micromachining and anodic bonding. The principle of the proposed micromachined alkali cell is based on an extremely compact sealed vacuum cavity of a few cubic millimeters containing caesium vapors, illuminated by a high-frequency modulated laser beam. The alkali cells are formed by sealing an etched silicon wafer between two glass wafers. The technique of cell filling involves the use of an alkali dispenser. The activation of cesium vapors is made by local heating of the dispenser below temperature range causing degradations of cesium vapor purity. Thus, the procedure avoids negative effects of cesium chemistry on the quality of cell surfaces and sealing procedure. To demonstrate the clock operation, cesium absorption as well as coherent population trapping resonance was measured in the cells.

Manufacturing method of semiconductor substrate, and manufacturing method of semiconductor device

Abstract: In a process of forming a single-crystalline semiconductor layer bonded to a glass substrate by low-temperature heat treatment, before a bonding and separation step in which the single-crystalline semiconductor layer is bonded to the glass substrate, the glass substrate is heated at a temperature higher than a heat temperature in the bonding and separation step. In a bonding step between the single-crystalline semiconductor layer and the glass substrate, the single-crystalline semiconductor layer is heated at a temperature close to a strain point of the glass substrate, specifically at a temperature in a range from minus 50° C. to plus 50° C. of a strain point. Accordingly, the glass substrate is subjected to heat treatment in advance at a temperature higher than the temperature close to the strain point, specifically, at a temperature higher than the temperature in a range from minus 50° C. to plus 50° C. of the strain point.

Adhesive bonding with SU-8 in a vacuum for capacitive pressure sensors

Abstract: This paper describes a method for fabricating capacitive pressure sensors through the use of adhesive bonding with SU-8 in a vacuum. The influence of different parameters on the bonding of structured wafers was investigated. It was found that pre-bake time, pumping time, and the thickness of the crosslink layer are the most important factors for successful bonding. Bonding quality was evaluated by inspection through the transparent glass of the sensor and through the use of an SEM photograph, with 90% of the area successfully bonded and an ultimate yield of 70% of the sensors. The measured bonding strength was 17.15 MPa and 19.6 MPa for wafers bonded in 80 °C and 100 °C, respectively. The pressure–capacitance characteristic test results show that this bonding process is a viable micro electro mechanical systems (MEMS) fabrication technology for cavity sealing in a vacuum.

Low-temperature wafer bonding of semiconductor substrates to metal substrates

Abstract: A method of wafer or substrate bonding a substrate made of a semiconductor material with a substrate made from a metallic material is disclosed. The method allows the bonding of the two substrates together without the use of any intermediate joining gluing, or solder layer(s) between the two substrates. The method allows the moderate or low temperature bonding of the metal and semiconductor substrates, combined with methods to modify the materials so as to enable low electrical resistance interfaces to be realized between the bonded substrates, and also combined with methods to obtain a low thermal resistance interface between the bonded substrates, thereby enabling various useful improvements for fabrication, packaging and manufacturing of semiconductor devices and systems.

Small gauge pressure sensor using wafer bonding and electrochemical etch stopping

Abstract: A gauge pressure sensor apparatus and a method of forming the same. A constraint wafer can be partially etched to set the diaphragm size, followed by bonding to a top wafer. The thickness of the top wafer is either the desired diaphragm thickness or is thinned to the desired thickness after bonding. The bonding of top wafer and constraint wafer enables electrochemical etch stopping. This allows the media conduit to be etched through the back of the constraint wafer and an electrical signal produced when the etching reaches the diaphragm. The process prevents the diaphragm from being over-etched. The invention allows the die size to be smaller than die where the diaphragm size is set by etching from the back side.

Theoretical and experimental analyses of atom diffusion characteristics on wire bonding interfaces

Abstract: The features of ultrasonic bonding interface were inspected by using a high resolution transmission electron microscope. Stress of ultrasonic bonding interface was analysed by the finite elements simulation. Results show that the high stress of bonding interface was caused by ultrasonic vibration, which increased the dislocation density inside the metal crystalline lattice which provides the fast diffusion channels, and provided driving force for atom inter-diffusion. 'Short-circuit diffusion' during ultrasonic bonding is more prominent than crystal diffusion. For the given ultrasonic bonding parameters, depth of atom diffusion at Au/Al interface of ultrasonic bonding was about 100–300 nm in several ten milliseconds, which forms the bonding strength of 0.65 N, and it is an inter-metallic compound of AuAl2. These will be helpful for further analysis.

Dislocation Networks Formed by Silicon Wafer Direct Bonding

Abstract: The paper reviews methods of hydrophobic wafer bonding. Hydrophobic surfaces are obtained by removing the oxide layer from the surfaces of crystalline silicon substrates. Bonding such surfaces causes the formation of a dislocation network in the interface. The structure of the dislocation network depends only on the misalignment (twist and tilt components). The different dislocation structures are discussed. Because wafer bonding offers a method to the reproducible formation of such networks, different applications are possible