Showing papers on "Anodic bonding published in 2013"

Ultra-thin DVS-BCB adhesive bonding of III-V wafers, dies and multiple dies to a patterned silicon-on-insulator substrate

Abstract: Heterogeneous integration of III-V semiconductor materials on a silicon-on-insulator (SOI) platform has recently emerged as one of the most promising methods for the fabrication of active photonic devices in silicon photonics. For this integration, it is essential to have a reliable and robust bonding procedure, which also provides a uniform and ultra-thin bonding layer for an effective optical coupling between III-V active layers and SOI waveguides. A new process for bonding of III-V dies to processed silicon-on-insulator waveguide circuits using divinylsiloxane-bis-benzocyclobutene (DVS-BCB) was developed using a commercial wafer bonder. This “cold bonding” method significantly simplifies the bonding preparation for machine-based bonding both for die and wafer-scale bonding. High-quality bonding, with ultra-thin bonding layers (<50 nm) is demonstrated, which is suitable for the fabrication of heterogeneously integrated photonic devices, specifically hybrid III-V/Si lasers.

Mechanisms for room temperature direct wafer bonding

Abstract: Reducing the temperature needed for high strength bonding which was and is driven by the need to reduce effects of coefficient of thermal expansion mismatch, reduce thermal budgets, and increase throughput has led to the development of plasma treatment procedures capable of bonding Si wafers below 300 °C with a bond strength equivalent to Si bulk. Despite being widely used, the physical and chemical mechanisms enabling low temperature wafer bonding have remained poorly understood. We developed an understanding of the beneficial surface modifications by plasma and a model based on short range low temperature diffusion through bonding experiments combined with results from spectroscopic ellipsometry, depth resolving Auger electron spectroscopy, and transmission electron microscopy measurements. We also present experimental results showing that even at room temperature reasonable bond strength can be achieved. We conclude that the gap closing mechanism is therefore a process which balances the lowering of the total energy by minimizing the sum of the free surface energy (maximizing the contact area between the surfaces) and strain energy in the oxide at the bond interface.

Oxygen Plasma and Humidity Dependent Surface Analysis of Silicon, Silicon Dioxide and Glass for Direct Wafer Bonding

Abstract: Surface and interface characteristics of substrates are critical for reliable wafer bonding. Understanding the elemental and compositional states of surfaces after various processing conditions is necessary when bonding dissimilar materials. Therefore, we investigated the elemental and compositional states of silicon (Si), silicon dioxide (SiO2) and glass surfaces exposed to oxygen reactive ion etching (O2 RIE) plasma followed by storage in controlled humidity and/or ambient atmospheric conditions to understand the chemical mechanisms in the direct wafer bonding. High-resolution X-ray Photoelectron Spectroscopy (XPS) spectra of O2 RIE treated Si, SiO2 and glass showed the presence of Si(-O)2 resulting in highly reactive surfaces. A considerable shift in the binding energies of Si(-O)2, Si(-O)4 and Si(-OH)x were observed only in Si due to plasma oxidation of the surface. The humidity and ambient storage of plasma activated Si and SiO2 increased Si(-OH)x due to enhanced sorption of hydroxyls. The amounts of Si(-O)2 and Si(-OH)x of Si varied in different humidity storage conditions which are attributed to crystal-orientation dependent surface morphology and oxidation. The O2 RIE plasma induced high surface reactivity and humidity induced Si(-OH)x can play an important role in the hydrophilic wafer bonding with low temperature heating. © 2013 The Electrochemical Society. [DOI: 10.1149/2.007312jss] All rights reserved.

Development of Particle Interface Bonding in Thermal Spray Coatings: A Review

Abstract: Thermal spray ceramic coatings deposited following the conventional routine exhibit a typical lamellar structure with a limited interface bonding ratio. The bonding between particles in the coating dominates coating properties and performance. In this review paper, the bonding formation at the interface between thin lamellae in the coating is examined. The effect of spray parameters on the bonding ratio is presented to reveal the main droplet parameters controlling bonding formation, which reveals that the temperature of the spray particle rather than its velocity dominates the bonding formation. The limitation to increase significantly the ceramic particle temperature inherent to the thermal spray process leads to the observation of a maximum bonding ratio of about 32%, while through controlling the surface temperature of the coating prior to molten droplet impact, the bonding at the lamellar interface can be significantly increased. Consequently, it is shown that with the proper selection of deposition conditions and control of the deposition temperature, the bonding ratio of ceramic deposits can be altered from a maximum of 32% for a conventional deposit to a maximum of 100%. Such wide adjustability of the lamellar bonding opens new possibilities for using thermal spray coatings in various applications requiring different microstructures and properties. The examination of recent studies shows that the bonding control makes it possible to fabricate porous deposits through surface-molten particles. Such an approach could be applied for the fabrication of porous materials, the deposition of high temperature abradable ceramic coatings, and for forming functional structured surfaces, such as a surface with super-hydrophobicity or a solid oxide fuel cell cathode interface with high specific surface area and high catalytic performance. Furthermore, complete interface bonding leads to crystalline structure control of individual splats through epitaxial grain growth.

Bonding of glass nanofluidic chips at room temperature by a one-step surface activation using an O2/CF4 plasma treatment

Abstract: A technical bottleneck to the broadening of applications of glass nanofluidic chips is bonding, due to the strict conditions, especially the extremely high temperatures (∼1000 °C) and the high vacuum required in the current glass-to-glass fusion bonding method. Herein, we report a strong, nanostructure-friendly, and high pressure-resistant bonding method, performed at room temperature (RT, ∼25 °C) for glass nanofluidic chips, using a one-step surface activation process with an O2/CF4 gas mixture plasma treatment. The developed RT bonding method is believed to be able to conquer the technical bottleneck in bonding in nanofluidic fields.

Influence of Joining Conditions on Bonding Strength of Joints: Efficacy of Low-Temperature Bonding Using Cu Nanoparticle Paste

Abstract: We investigated a new low-temperature bonding process utilizing Cu nanoparticle paste without addition of sintering promoter. Joint bonding strengths above 30 MPa were achieved even at a low bonding temperature of 250oC. We attribute the higher bonding strengths of joints fabricated using the vacuum preheating process to the rapid progression of Cu nanoparticle sintering due to the activated nanoparticle surface at lower temperatures. The increase in bonding strength depended on the applied pressure, in addition to the bonding temperature. The formation of a dimple-like morphology was confirmed in the ductile fracture area. This indicated that the joint bonded strongly with the bonding layer, in agreement with the results of bonding tests carried out on strongly bonded joints. The bonding ability of the joints obtained using Cu nanoparticle paste could be improved by controlling the joint fabrication conditions.

Critical bonding temperature for the splat bonding formation during plasma spraying of ceramic materials

Abstract: Controllable formation of splat bonding in thermally sprayed coatings is essential to fulfill requirements of versatile coating applications, because the bonding influences most of the coating properties. The splat bonding formation in single-layered and multi-layered Al 2 O 3 and YSZ splats was examined at different deposition temperatures to reveal the factors dominating the splat bonding formation. Results show that the splat interface bonding was significantly influenced by the deposition temperature. There is a critical bonding temperature for the formation of the effective splat interface bonding in plasma-sprayed ceramic coating. The critical bonding temperature depends on coating materials. It is found that the critical bonding temperature is ~ 300 °C or ~ 600 °C for Al 2 O 3 or YSZ, respectively. It will be shown that the critical bonding temperature concept can be used to explain qualitatively reasonably the lamellar bonding formation during multi-splats and coating deposition.

Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging

Abstract: We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 mΩ. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test.

Silane modification of glass and silica surfaces to obtain equally oil‐wet surfaces in glass‐covered silicon micromodel applications

Abstract: [1] Wettability is a key parameter influencing capillary pressures, permeabilities, fingering mechanisms, and saturations in multiphase flow processes within porous media. Glass-covered silicon micromodels provide precise structures in which pore-scale displacement processes can be visualized. The wettability of silicon and glass surfaces can be modified by silanization. However, similar treatments of glass and silica surfaces using the same silane do not necessarily yield the same wettability as determined by the oil-water contact angle. In this study, surface cleaning pretreatments were investigated to determine conditions that yield oil-wet surfaces on glass with similar wettability to silica surfaces treated with the same silane, and both air-water and oil-water contact angles were determined. Borosilicate glass surfaces cleaned with standard cleaning solution 1 (SC1) yield intermediate-wet surfaces when silanized with hexamethyldisilazane (HMDS), while the same cleaning and silanization yields oil-wet surfaces on silica. However, cleaning glass in boiling concentrated nitric acid creates a surface that can be silanized to obtain oil-wet surfaces using HMDS. Moreover, this method is effective on glass with prior thermal treatment at an elevated temperature of 400°C. In this way, silica and glass can be silanized to obtain equally oil-wet surfaces using HMDS. It is demonstrated that pretreatment and silanization is feasible in silicon-silica/glass micromodels previously assembled by anodic bonding, and that the change in wettability has a significant observable effect on immiscible fluid displacements in the pore network.

Al-Al thermocompression bonding for wafer-level MEMS packaging

Abstract: The Al-Al thermocompression bonding is studied on test structures suitable for wafer level packaging of MEMS devices. Si wafers with protruding frame structures have been bonded to planar Si wafers all covered with a 1 μm sputtered Al film. The varied bonding process variables were temperature (400 °C-550 °C), bonding force (18-36 kN) and frame widths (100 μm, 200 μm, rounded or sharp corners). The delamination caused by dicing and pull tests is systematically studied. It is concluded that bonding is incomplete at 400 °C, with a low dicing yield. The quality of the bonding is increased by increasing bonding temperature and force as expected. The fractured surfaces and the bonding strength have been studied in detail. The test structures showed an average strength of 20-50 MPa for bonding at or above 450 °C. The current study indicates that strong Al-Al thermocompression bonds can be achieved at or above 450 °C for a typical MEMS bond frame.

Three-dimensional (3D) integrated circuit with enhanced copper-to-copper bonding

Abstract: At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device wafer and on the at least one metal adhesion layer. The first and second device wafers are then bonded together. The bonding includes heating the devices wafers to a temperature of less than 400° C., with or without, application of an external applied pressure. During the heating, the two Cu surfaces are bonded together and the at least one metal adhesion layer gets oxygen atoms from the two Cu surfaces and forms at least one metal oxide bonding layer between the Cu surfaces.

Glass film cleaving method and glass film laminate

Abstract: A glass film cleaving method includes cleaving a full-body of a glass film having a thickness of 200 μm or less by propagating an initial crack along a preset cleaving line through heating of the glass film with a laser beam followed by subsequent cooling of the glass film. The method also includes manufacturing a glass film laminate by setting a surface roughness Ra of a surface of the glass film to contact a support glass, which supports the glass film, and a surface of the support glass to contact the glass film to 2.0 nm or less, and by bringing the surfaces of the glass film and the support glass into surface contact with each other, followed by the cleaving.

A Glass-in-Silicon Reflow Process for Three-Dimensional Microsystems

Abstract: This paper reports a new batch-mode fabrication process that combines glass and silicon into a single wafer. The technique requires only a single mask to lithographically define recesses in silicon using deep reactive ion etching. The patterned silicon wafer is anodically bonded to a glass wafer, and a high-temperature step reflows the glass into this silicon mold. The reflowed wafer stack is then planarized and thinned. Through-glass vias can be realized in this manner while additional process-flow modifications enable features such as molded cavities in the glass. A capacitive pressure sensor and a hermetically sealed resonator are described to illustrate applications of the process. Finally, a three dimensional packaging technique for implantable biomedical microsystems is shown by vertically stacking glass-in-silicon wafers.

Wafer-level SLID bonding for MEMS encapsulation

Abstract: Hermetic packaging is often an essential requirement to enable proper functionality throughout the device’s lifetime and ensure the optimal performance of a micro electronic mechanical system (MEMS) device. Solid-liquid interdiffusion (SLID) bonding is a novel and attractive way to encapsulate MEMS devices at a wafer level. SLID bonding utilizes a low-melting-point metal to reduce the bonding process temperature; and metallic seal rings take out less of the valuable surface area and have a lower gas permeability compared to polymer or glass-based sealing materials. In addition, ductile metals can adopt mechanical and thermo-mechanical stresses during their service lifetime, which improves their reliability. In this study, the principles of Au-Sn and Cu-Sn SLID bonding are presented, which are meant to be used for wafer-level hermetic sealing of MEMS resonators. Seal rings in 15.24 cm silicon wafers were bonded at a width of 60 μm, electroplated, and used with Au-Sn and Cu-Sn layer structures. The wafer bonding temperature varied between 300 °C and 350 °C, and the bonding force was 3.5 kN under the ambient pressure, that is, it was less than 0.1 Pa. A shear test was used to compare the mechanical properties of the interconnections between both material systems. In addition, important factors pertaining to bond ring design are discussed according to their effects on the failure mechanisms. The results show that the design of metal structures can significantly affect the reliability of bond rings.

Glass articles and methods for controlled bonding of glass sheets with carriers

Abstract: Surface modification layers and associated heat treatments, that may be provided on a sheet, a carrier, or both, to control both room-temperature van der Waals (and/or hydrogen) bonding and high temperature covalent bonding between the thin sheet and carrier. The room-temperature bonding is controlled so as to be sufficient to hold the thin sheet and carrier together during vacuum processing, wet processing, and/or ultrasonic cleaning processing, for example. And at the same time, the high temperature covalent bonding is controlled so as to prevent a permanent bond between the thin sheet and carrier during high temperature processing, as well as maintain a sufficient bond to prevent delamination during high temperature processing.

Interfacial Characteristics and Dynamic Process of Au- and Cu-Wire Bonding and Overhang Bonding in Microelectronics Packaging

Abstract: Microstructure characteristics of Cu-wire bonding interface are investigated first by using the X-ray microdiffractometer, and the dynamic process of Cu- and Au-wire overhang bonding is recorded first with a high-speed camera system. It was found that the success rate of Cu-wire bonding is lower than that of Au-wire bonding, the formation of Cu-Al intermetallic compounds (IMCs) is more difficult than that of Au-Al IMCs, and the impact and deflection of Cu-wire overhang bonding process are much bigger than those of Au-wire overhang bonding process and affect bonding performance. In order to improve the bondability of Cu-wire bonding and overhang bonding, an approach with thick Al pad on the die which reduces its hardness is more compliant during Cu bonding process; another idea is to activate the formation of Cu-Al IMCs by increasing the energy. The effectiveness of the suggested approach is confirmed. In particular, Al2Cu and Al4Cu9 IMCs can form within 18 ms due to diffusion and reaction activated by high thermal (to 340 ° C) combined with ultrasonic energy at the bonding interface, and the success rate and strength of Cu-wire bonding increased significantly when Cu-Al IMCs form. For overhang bonding, the approach with thick Al layer improves dynamics features of hard Cu-wire overhang bonding process; thereby, it enhances the performance of Cu-wire overhang bonding.

Effects of surface treatment on the bonding quality of wafer-level Cu-to-Cu thermo-compression bonding for 3D integration

Abstract: Various surface treatments are applied for surface oxide removal prior to wafer-level Cu-to-Cu thermo-compression bonding and the bonding quality is systematically analyzed in this work. Three methods are investigated: self-assembled monolayer (SAM) passivation, forming gas annealing and acetic acid wet cleaning. The surface conditions are carefully examined including roughness, contact angle and x-ray photoelectron spectroscopy (XPS) scan. The wafer pairs are bonded at 250??C under a bonding force of 5500?N for a duration of 1?h in a vacuum environment. The bonding medium consists of a Cu (300?nm) bonding layer and a Ti (50?nm) barrier layer. The bonding quality investigation consists of two parts: hermeticity based on helium leak test and mechanical strength using four-point bending method. Although all samples under test with different surface treatment methods present an excellent hermetic seal and a robust mechanical support, the measurement results show that samples bonded after SAM passivation exhibit the best hermeticity and bonding strength for 3D integration application.

Atomic-plane-thick reconstruction across the interface during heteroepitaxial bonding of InP-clad quantum wells on silicon

Abstract: An oxide-free heteroepitaxial bonding of InP-clad GaInAs quantum wells on Si showing an atomic-plane-thick reconstruction across the InP-Si interface and no degradation of the quantum wells luminescence is demonstrated. Several InP surface preparation procedures have been investigated to ensure an oxide-free bonding. Such a bonding procedure without oxide or metal mediation allows embedding very-high-index-contrast nanostructuration within optic and optoelectronic integrated devices, thus enabling tailored designs enhancing dedicated optical functions. Heteroepitaxial bonding is also similarly obtained on nanopatterned Si surface.

Methods for hybrid wafer bonding

Abstract: Methods for hybrid wafer bonding. In an embodiment, a method is disclosed that includes forming a metal pad layer in a dielectric layer over at least two semiconductor substrates; performing chemical mechanical polishing on the semiconductor substrates to expose a surface of the metal pad layer and planarize the dielectric layer to form a bonding surface on each semiconductor substrate; performing an oxidation process on the at least two semiconductor substrates to oxidize the metal pad layer to form a metal oxide; performing an etch to remove the metal oxide, recessing the surface of the metal pad layer from the bonding surface of the dielectric layer of each of the at least two semiconductor substrates; physically contacting the bonding surfaces of the at least two semiconductor substrates; and performing a thermal anneal to form bonds between the metal pads of the semiconductor substrates. Additional methods are disclosed.

Fabrication of an hermetically packaged silicon resonator on LTCC substrate

Abstract: The design, fabrication and packaging process of silicon resonators capable of the integration of LSI (Large Scale Integration) have been developed on the basis of packaging technology using an LTCC (Low Temperature Co-fired Ceramic) substrate. The structures of silicon resonators are defined by deep reactive ion etching (DRIE) on a silicon on insulator (SOI) wafer and then transferred onto the LTCC substrate and hermetically sealed by anodic bonding technique. The measured resonant frequency of a micromechanical bulk acoustic mode silicon resonator after packaging at 0.02 Pa is 20.24 MHz with a quality factor of 50,600.

Lifetime improvement of micro-fabricated alkali vapor cells by atomic layer deposited wall coatings

Abstract: Alumina (Al 2 O 3 ), silicon dioxide (SiO 2 ) and titanium dioxide (TiO 2 ) films were examined for their suitability as a protection coating for micro-fabricated cesium vapor cells. The layers were deposited by atomic layer deposition (ALD). This technique enables the deposition of pinhole-free passivation layers with a low roughness, a high conformality and a high homogeneity, even at three-dimensional surfaces. It is shown that Al 2 O 3 and SiO 2 films, in contrast to TiO 2 films, do not hamper anodic bonding up to thicknesses of 20 nm. The resistance enhancement of the vapor cells by means of the implementation of the ALD films is demonstrated by absorption measurements of the cesium D1 line. SiO 2 coatings showed no effects on the resistance of the vapor cells against the reducing behavior of cesium. In contrast, Al 2 O 3 coatings improved the resistance of the vapor cells by a factor of ~ 100.

Anodic bonded 2D semiconductors: from synthesis to device fabrication

Abstract: Two-dimensional semiconductors are increasingly relevant for emergent applications and devices, notably for hybrid heterostructures with graphene. We fabricate few-layer, large-area (a few tens of microns across) samples of the III-VI semiconductors GaS, GaSe and InSe using the anodic bonding method and characterize them by simultaneous use of optical microscopy, atomic force microscopy and Raman spectroscopy. Two-terminal devices with a gate are constructed to show the feasibility of applications based on these.

Chip bonding structure and manufacturing method thereof

Abstract: A chip bonding structure at least includes a first substrate, a second substrate opposite to the first substrate, and a copper bonding structure sandwiched in between the first and the second substrates. A Cu—Cu bonding interface is within the copper bonding structure and is characterized with combinations of protrusions and recesses, and the copper crystallization orientation at one side of the Cu—Cu bonding interface is different from that at another side.

Room-Temperature Cu Microjoining with Ultrasonic Bonding of Cone-Shaped Bump

Abstract: Room-temperature Cu–Cu bonding was realized by applying ultrasonic vibration together with compression force to the bonding of a cone-shaped bump. The size of the bump was about 10 µm. The connection pitch was 20 µm. Mechanical characterization showed that the bonding strength increases with vibration amplitude and depends on the thickness of the counter electrode made of Cu. The thickness dependence of the bonding strength was found to be caused by an increase in the surface roughness of the counter electrode. It was shown that the bonding strength meets the requirement from application to products. Electrical characterization using a daisy-chain connection test demonstrated that more than 10,000 pins on a chip can be connected with a sufficiently low resistance.

Fabricating 3D integrated CMOS devices by using wafer stacking and via-last TSV technologies

Abstract: A three-layer-stacked wafer with CMOS devices was fabricated for the first time by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings both seamless copper bonding and void-less underfilling in face-to-face (F2F) and back-to-face (B2F) configurations. The backside-via-last TSV processes provide electrical connection between a TSV and copper/low-k interconnects without causing low-k damage. The low capacitance (around 40 fF) of the TSVs results in the highest level of transmission performance (15 Tbps/W) so far. Additionally, according to ring-oscillator measurements, the keep-out-zone (KOZ) is up to 2 μm from a TSV. This extremely small KOZ is mainly attributed to low residual stress in the silicon surrounding a TSV (i.e., below 50 MPa at 2 μm from a TSV edge).

Low-Temperature Cu-Cu Wafer Bonding

Abstract: Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level. The process requires typically bonding temperatures of ~400{degree sign}C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve some issues regarding wafer-to-wafer misalignment after bonding and to minimize thermo-mechanical stresses. Low-temperature (LT) Cu-Cu wafer bonding was successfully demonstrated at 175{degree sign}C. The bond quality, bond strength, metal interface layers microstructure and chemical composition of Cu-Cu wafer pairs bonded under different process conditions were investigated. Experimental results on various Cu native oxide methods evaluation as well as results obtained for various bonding and annealing temperatures are presented.

Glass and methods of making glass articles

Abstract: Surface modification layers (30) and associated heat treatments, that may be provided on a sheet (20), a carrier (10), or both, to control both room-temperature van der Waals (and/or hydrogen) bonding and high temperature covalent bonding between the thin sheet and carrier. The room-temperature bonding is controlled so as to be sufficient to hold the thin sheet and carrier together during vacuum processing, wet processing, and/or ultrasonic cleaning processing, for example. And at the same time, the high temperature covalent bonding is controlled so as to prevent a permanent bond between the thin sheet and carrier during high temperature processing, as well as maintain a sufficient bond to prevent delamination during high temperature processing.

Methods for Hybrid Wafer Bonding Integrated with CMOS Processing

Abstract: Methods for forming an integrated device using CMOS processing with wafer bonding In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit Additional methods are disclosed

Self-Packaging Fabrication of Silicon–Glass-Based Piezoresistive Pressure Sensor

Abstract: A self-packaged piezoresistive pressure sensor was fabricated using a silicon-glass anodic bonding technique. The Wheatstone bridge piezoresistive sensing configuration was located on the lower surface of the silicon diaphragm and was vacuum sealed in a Si-glass cavity, and the embedded Al feedthrough lines at the Si-glass interface were used to realize the electrical connections between the piezoresistive sensing elements and hybrid metal electrode pads through Al vias and heavily doped diffusion zones. The pressure sensors demonstrate comparable performance characteristics, but a more simple process and low cost in comparison with the commercial Si-based piezoresistive pressure sensor. Due to the self-packaging protection, the pressure sensors are capable of handling harsh environments.