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Showing papers on "Anodic bonding published in 2015"


Journal ArticleDOI
TL;DR: Direct Cu-to-Cu bonding was achieved at temperatures of 150–250 °C using a compressive stress of 100 psi (0.69 MPa) held for 10–60 min at 10−3 torr.
Abstract: Direct Cu-to-Cu bonding was achieved at temperatures of 150–250 °C using a compressive stress of 100 psi (0.69 MPa) held for 10–60 min at 10−3 torr. The key controlling parameter for direct bonding is rapid surface diffusion on (111) surface of Cu. Instead of using (111) oriented single crystal of Cu, oriented (111) texture of extremely high degree, exceeding 90%, was fabricated using the oriented nano-twin Cu. The bonded interface between two (111) surfaces forms a twist-type grain boundary. If the grain boundary has a low angle, it has a hexagonal network of screw dislocations. Such network image was obtained by plan-view transmission electron microscopy. A simple kinetic model of surface creep is presented; and the calculated and measured time of bonding is in reasonable agreement.

123 citations


Journal ArticleDOI
TL;DR: In this paper, a fabrication process based on direct wafer bonding was proposed for high efficient III-V/Si triple-junction solar cells, which enabled a transparent and electrically conductive interface.
Abstract: Highly efficient III–V/Si triple-junction solar cells were realized by a fabrication process based on direct wafer bonding: Ga0.51In0.49P/GaAs dual-junction solar cells were grown inverted by metal organic vapor phase epitaxy on GaAs substrates and bonded to separately fabricated Si solar cells. The fast atom beam activated direct wafer bond between highly doped n-Si and n-GaAs enabled a transparent and electrically conductive interface. Challenges arising from the different thermal expansion coefficients of Si and the III–V semiconductors were circumvented, as the bonding was performed at moderate temperatures of 120 °C. The external quantum efficiency and current–voltage characteristics of the wafer-bonded triple-junction solar cells were thoroughly investigated, and a maximum efficiency of 30.0% was found for a concentration factor of 112.

91 citations


Journal ArticleDOI
TL;DR: This paper introduces a simplified fabrication method for vacuum-sealed capacitive micromachined ultrasonic transducer arrays using anodic bonding, which combines the advantages of a patterned metal bottom electrode on an insulating substrate, specifically low parasitic series resistance and low parasitic shunt capacitance.
Abstract: This paper introduces a simplified fabrication method for vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT) arrays using anodic bonding. Anodic bonding provides the established advantages of wafer-bondingbased CMUT fabrication processes, including process simplicity, control over plate thickness and properties, high fill factor, and ability to implement large vibrating cells. In addition to these, compared with fusion bonding, anodic bonding can be performed at lower processing temperatures, i.e., 350°C as opposed to 1100°C; surface roughness requirement for anodic bonding is more than 10 times more relaxed, i.e., 5-nm rootmean- square (RMS) roughness as opposed to 0.5 nm for fusion bonding; anodic bonding can be performed on smaller contact area and hence improves the fill factor for CMUTs. Although anodic bonding has been previously used for CMUT fabrication, a CMUT with a vacuum cavity could not have been achieved, mainly because gas is trapped inside the cavities during anodic bonding. In the approach we present in this paper, the vacuum cavity is achieved by opening a channel in the plate structure to evacuate the trapped gas and subsequently sealing this channel by conformal silicon nitride deposition in the vacuum environment. The plate structure of the fabricated CMUT consists of the single-crystal silicon device layer of a silicon-on-insulator wafer and a thin silicon nitride insulation layer. The presented fabrication approach employs only three photolithographic steps and combines the advantages of anodic bonding with the advantages of a patterned metal bottom electrode on an insulating substrate, specifically low parasitic series resistance and low parasitic shunt capacitance. In this paper, the developed fabrication scheme is described in detail, including process recipes. The fabricated transducers are characterized using electrical input impedance measurements in air and hydrophone measurements in immersion. A representative design is used to demonstrate immersion operation in conventional, collapse-snapback, and collapse modes. In collapsemode operation, an output pressure of 1.67 MPa pp is shown at 7 MHz on the surface of the transducer for 60-Vpp, 3-cycle sinusoidal excitation at 30-V dc bias.

65 citations


Patent
20 Aug 2015
TL;DR: In this paper, the authors proposed a method of forming a hybrid bonding structure by depositing an etch stop layer over surface of a substrate, wherein the substrate comprises a conductive structure, and the etch stopslayer contacts the conductive structures.
Abstract: A method of forming a hybrid bonding structure includes depositing an etch stop layer over surface of a substrate, wherein the substrate comprises a conductive structure, and the etch stop layer contacts the conductive structure. The method further includes depositing a dielectric material over the etch stop layer. The method further includes depositing a first diffusion barrier layer over the dielectric material. The method further includes forming an opening extending through the etch stop layer, the dielectric material and the diffusion barrier layer. The method further includes lining the opening with a second diffusion barrier layer. The method further includes depositing a conductive pad on the second diffusion barrier layer in the opening, wherein a surface of the first diffusion barrier layer is aligned with a surface of the conductive pad.

52 citations


Journal ArticleDOI
TL;DR: In this article, a low-temperature direct Cu bonding structure is demonstrated using metal passivated layers with the protection of Cu bonding layer, the bonding temperature can be reduced to meet low thermal budget requirement Direct wafer-level Cu bond scheme with Pd passivation is successfully demonstrated at 150 °C.
Abstract: In this paper, one low-temperature direct Cu bonding structure is demonstrated using metal passivated layers With the protection of Cu bonding layer, the bonding temperature can be reduced to meet low thermal budget requirement Direct wafer-level Cu bond scheme with Pd passivation is successfully demonstrated at 150 °C Electrical performance along with the material analysis and reliability tests of passivated Cu bonded structures is presented Furthermore, reliability assessments, including current stressing, temperature cycling, and unbiased highly accelerated stress test, imply excellent stability without electrical degradation Diffusion behavior between passivation Pd and Cu layers is surveyed, and the corresponding mechanism is discussed as well The low-temperature Cu/Pd–Pd/Cu bonded structure presents good bond quality and electrical performance, indicating a great potential for 3-D integration applications

51 citations


Patent
19 May 2015
TL;DR: Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described in this paper, as well as methods of fabricating such devices, which may involve two separate wafer bonding steps.
Abstract: Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

51 citations


Journal ArticleDOI
TL;DR: In this article, a new method for wafer-level hermetic packaging of MEMS devices using a relatively low temperature anodic bonding technique applied to the recently developed advanced MEMS (aMEMS) process is presented.
Abstract: This paper presents a new method for wafer-level hermetic packaging of MEMS devices using a relatively low temperature anodic bonding technique applied to the recently developed advanced MEMS (aMEMS) process. The aMEMS process uses vertical feedthroughs formed on an SOI cap wafer, eliminating the need for any complex via-refill or trench-refill steps while forming the vertical feedthroughs. The hermetic sealing process is achieved at 350 °C by using an anodic bonding potential of 600 V. The bonding process does not require any sealing material on neither the cap nor the sensor wafer. The packaging yield is experimentally verified to be 94% for 4 wafers packaged up to date, and the cavity pressure is measured to be as low as 1 mTorr with successfully activated Titanium thin film getter. The cavity pressure can be set to different levels ranging from 1 mTorr up to 5 Torr, simply by varying the outgassing period and utilization of the getter material, enabling the proposed method be used for various types of MEMS devices with different pressure requirements. The pressure inside the encapsulated cavities has been monitored for 6 months since the first prototypes, and it is observed that pressure is stable below 5 mTorr throughout this period. The shear strength of 6 packages is measured to be above 10 MPa, whereas the shear failure occurs not at the bonding interface but the vertical feedthroughs, which have lower strength compared to the bonding region. The robustness of the packages is tested by subjecting them to cyclic thermal tests between 100 °C and 25 °C, and no degradation is observed in the hermeticity of the packages at the end of this period. The vacuum level of the packages is also verified to be unchanged by storing the packages at 150 °C for 24 h. Moreover, it is experimentally verified that the hermeticity of the packaged chips can withstand ultra-high temperature shocks as high as 400 °C for 5 min.

47 citations


Journal ArticleDOI
TL;DR: In this article, the authors showed that at a sufficiently low bonding temperature of 700°C and a bonding duration of 4h, the joint reaches a reasonable high ductility and toughness especially at elevated test temperature of 550°C with elongation to fracture of 20% and mean absorbed Charpy impact energy of 2

46 citations


Journal ArticleDOI
TL;DR: In this article, the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200°C, and the results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled.
Abstract: The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The mode...

44 citations


Journal ArticleDOI
TL;DR: In this article, a thermal poling process on a specific borosilicate glass composition can yield a surface with tailored physical and chemical properties, such as the ability to control glass surface reactivity at different length enables key properties required for future smart substrates.
Abstract: The ability to control glass surface reactivity at different length enables key properties required for future “smart substrates”. Employing a thermal poling process on a specific borosilicate glass composition can yield a surface with tailored physical and chemical properties. This work shows that during poling, alkali contained in the glass matrix migrates from the anode to the cathode side of the specimen, yielding the formation of an alkali-depleted layer under the anode. We have shown that this process is responsible for structural changes in the glass network and the formation of a frozen electric field within the glass. Network reorganization is linked to the creation of BO3 units, which replace BO4– entities upon migration of the alkali ions. The resulting newly charged borate structure leads to a measurable change in the glass’ affinity to atmospheric water, being attracted to the poled anodic zone. Such spatial control of surface hydrophilicity can aid in the creation of tailored surface functio...

41 citations


Journal ArticleDOI
TL;DR: In this paper, surface-activated bonding using an argon fast atom beam was applied to the bonding of gallium arsenide (GaAs) and silicon carbide (SiC) wafers.
Abstract: Thermal management of high-power semiconductor lasers is of great importance since the output power and beam quality are affected by the temperature rise of the gain region. Thermal simulations of a vertical-external-cavity surface-emitting laser by a finite-element method showed that the solder layer between the semiconductor thin film consisting of the gain region and a heat sink has a strong influence on the thermal resistance and direct bonding is preferred to achieve effective heat dissipation. To realize thin-film semiconductor lasers directly bonded on a high-thermal-conductivity substrate, surface-activated bonding using an argon fast atom beam was applied to the bonding of gallium arsenide (GaAs) and silicon carbide (SiC) wafers. The GaAs/SiC structure was demonstrated in the wafer scale (2 in. in diameter) at room temperature. The cross-sectional transmission electron microscopy observations showed that void-free bonding interfaces were achieved.

Journal ArticleDOI
TL;DR: In this article, the authors evaluated die-attach bonding using a transient liquid phase (TLP) bonding method on a Cu/In, Au/In and Cu-Sn3Ag metal stack.
Abstract: Die-attach bonding was evaluated using a transient liquid phase (TLP) bonding method on a Cu/In, Au/In and Cu-Sn3Ag metal stack. TLP bonding is a relatively low cost process since thin layers of material are used and, at the same time, has higher reliability due to the good thermal resistance of the intermetallic compounds (IMCs) formed. The bonded samples were aged at 300°C for 500 h and thermal cycled from −40°C to 125°C for 500 cycles. The results showed that the shear strength of the Cu/In joint was higher than that of the Au/In joint with increasing aging time. Cu/In specimens on a ceramic substrate also showed good reliability results during the thermal cycling test. Even though Cu/In TLP bonding is not popular in conventional electronics, it is suitable for high temperature electronics due to the simplicity of the IMC formation.

Journal ArticleDOI
TL;DR: In this article, a modified surface activated bonding (SAB) method was used to achieve strong SiC wafer bonding with tensile strength greater than 32 MPa at room temperature under 5 kN force for 300 s.
Abstract: 4H-SiC wafer bonding has been achieved by the modified surface activated bonding (SAB) method without any chemical-clean treatment and high temperature annealing. Strong bonding between the SiC wafers with tensile strength greater than 32 MPa was demonstrated at room temperature under 5 kN force for 300 s. Almost the entire wafer has been bonded very well except a small peripheral region and few voids. The interface structure was analyzed to verify the bonding mechanism. It was found an amorphous layer existed as an intermediate layer at the interface. After annealing at 1273 K in vacuum for 1 h, the bonding tensile strength was still higher than 32 MPa. The interface changes after annealing were also studied. The results show that the thickness of the amorphous layer was reduced to half after annealing.

Proceedings ArticleDOI
23 Nov 2015
TL;DR: The evaluation result of 4 layer stacked IC which was bonded using thermal compression bonder (TCB) is reported and it was confirmed that the voidless and good solder joints were possible by reducing the temperature difference in a stacking direction.
Abstract: The evaluation result of 4 layer stacked IC which was bonded using thermal compression bonder (TCB) is reported. The throughput can be remarkably improved because chips of multi-layer can be pre bonded by using non-conductive film (NCF) which is pre-applied adhesive and can be thermally pressed at a time. To realize this process, we stacked the 4 chips having through silicon via (TSV) on a Si substrate and evaluated the connectibility. As the evaluation after bonding, wettability of a solder by cross-section observation and a void in NCF layer by constant depth mode scanning acoustic microscope (C-SAM) observation were confirmed. As a result, it was confirmed that the voidless and good solder joints were possible by reducing the temperature difference in a stacking direction. For the evaluation, we used the TEG of 6 mm × 6 mm × 0.05 mm size which has more than 15,000 bumps of 12 µm height and 15 µm diameter. It was also demonstrated that gang bonding for a plurality of pre bonded chips formed on a substrate was possible by using the novel bonding attachment which accepts the thicknesses difference of 5 µm.

Journal ArticleDOI
TL;DR: Wafer alignment during stacking process was found to be affected by several factors like non-uniform bump height, the spacers in a bonding fixture, and wafer warpage as mentioned in this paper.

Journal ArticleDOI
TL;DR: In this paper, the effect of the bonding temperature and environment (air and N 2 ) on the joint strength of Ag nanoporous bonding (NPB) on electroless nickel/immersion gold finished Cu disks was investigated.
Abstract: Ag nanoparticle sintering has received much attention as an alternative joining method to lead-based soldering for high temperature electronic applications. However, there are still certain issues with this method, such as difficulties of in controlling the joining layer thickness and the occurrence of unexpected voids resulting from solvent evaporation. In this study, the effect of bonding temperature (200–400 °C) and environment (air and N 2 ) on the joint strength of Ag nanoporous bonding (NPB) on electroless nickel/immersion gold finished Cu disks was investigated. A nanoporous Ag sheet fabricated using dealloying method from an Al–Ag precursor was adopted as the insert material. The NPB was conducted at various temperatures (200–400 °C) for 30 min at a pressure of 20 MPa in both air and N 2 environments. The joint strength of NPB was closely related with the microstructure of the Ag layer and the fracture mode of the joint, and increased with increasing bonding temperature through the formation of strong interface and a coarsened Ag layer. The effect of the bonding environment was not significant, except in the case of bonding temperature of 400 °C.

Proceedings ArticleDOI
01 Aug 2015
TL;DR: The low temperature permanent wafer bonding is studied on the plasma enhanced chemical vapour deposited dielectrics with modified surface properties characterized by using water wettability, hydrophilicity as well as the surface roughness.
Abstract: The low temperature permanent wafer bonding is studied on the plasma enhanced chemical vapour deposited dielectrics. Three types of dielectric material (SiOx, SiOxNy, SiCxNy) were prepared by the conventional CMOS interconnection process which includes the thermal annealing and chemical mechanical polishing step. The plasma treatment generated by different inert gas was evaluated to activate the dielectric surface prior to wafer bonding. The modified surface properties were characterized by using water wettability, hydrophilicity as well as the surface roughness. The obtained surface properties have been discussed with the interface bonding energy.

Journal ArticleDOI
TL;DR: In this article, the formation of nanoscale surface relief on the anodic surface of an alkali-silicate glass in the course of thermal poling in open anode configuration and related structural/compositional changes in subanodic region of the glass are studied.
Abstract: Formation of nanoscale surface relief on the anodic surface of an alkali-silicate glass in the course of thermal poling in open anode configuration and related structural/compositional changes in subanodic region of the glass are studied. Surface of poled glass beneath anodic electrode goes down relatively to the unpoled glass area. The depth of the relief increases linearly with the electric charge transferred through the glass in poling till ~ 200 mC/cm2 charge density, when the depth saturates at ~ 190 nm. While the depth-charge dependence is linear, the glass surface keeps initial quality, and the saturation region corresponds to arising voids and channels directed in the depth of the poled glass. Our evaluations show that the volume difference resulting from the replacement of alkaline and alkaline earth ions by hydrogen is insufficient to provide observed relief. Raman scattering measurements evidence that the poling induces rearrangement of the structure of the glass via losing non-bridging oxygen atoms and forming molecular oxygen. This makes the glass very similar to silica one. These processes are mainly responsible for the surface relief formation.

Journal ArticleDOI
TL;DR: In this article, the bonding mechanism of lead-free solder to glass by ultrasonic assisted soldering was examined using scanning electron microscopy (SEM) and TEM, and the effects of ultrasonication, the elements and oxygen concentration in the solder on the bonding behavior were also investigated.

Journal ArticleDOI
TL;DR: In this paper, the mechanical and electrical characteristics of Ge/Ge interfaces prepared by room-temperature surface-activated bonding (SAB) were reported. And the current-voltage characteristics and microstructures of bonded interfaces formed by SAB and lowtemperature plasma activation bonding (PAB) are compared.
Abstract: This paper reports the mechanical and electrical characteristics of Ge/Ge interfaces prepared by room-temperature surface-activated bonding (SAB). Bonded Ge/Ge wafer pairs with high bonding strength equivalent to that of the bulk material were achieved without any heat treatment. It was found that the bonding of Ge wafers was not sensitive to the background vacuum pressure in a wafer-bonding chamber compared with the bonding of Si wafers. The current–voltage characteristics and microstructures of bonded interfaces formed by SAB and low-temperature plasma activation bonding (PAB) were compared. It was demonstrated that junctions with very low resistivity can be obtained by SAB at room temperature.

Journal ArticleDOI
TL;DR: In this paper, a novel process for the fabrication of capacitive micromachined ultrasonic transducer (CMUT) arrays with isolation trenches using anodic bonding technique is presented.
Abstract: This paper presents a novel process for the fabrication of capacitive micromachined ultrasonic transducer (CMUT) arrays with isolation trenches using anodic bonding technique. The developed fabrication process is easy, stiction-free, repeatable, reliable, requires low-temperature ( $1 \times 5, 5 \times 5$ , and $10 \times 10$ CMUT arrays. CMUT cells were designed using MEMSCAD tool CoventorWare. The fabricated devices have been characterized using nanovibration analyzer, and the resonance frequency is found to be $\sim 1.5$ MHz.

Journal ArticleDOI
TL;DR: In this paper, a new polymer bonding method using thin Si and Fe layers and the surface activated bonding (SAB) method are applied to bond poly(ethylene naphthalate) (PEN) films to each other.
Abstract: A sealing method for polymer substrates to be used in flexible electronics is studied. For this application, a low-temperature sealing method that achieves flexible bonding of inorganic bonding material is required, but no conventional technique satisfies these requirements simultaneously. In this study, a new polymer bonding method using thin Si and Fe layers and the surface activated bonding (SAB) method are applied to bond poly(ethylene naphthalate) (PEN) films to each other. PEN films can be bonded via the proposed method without voids at room temperature, and the bonded samples are bendable. The adhesion strength of the bonded samples is so strong that fracture occurs in the polymer bulk rather than at the bond interface. Investigations of the bonded samples by transmission electron microscopy (TEM) and Fourier-transform infrared spectroscopy (FTIR) reveal that bonding is achieved by chemical interactions between the polymer surface and deposited atoms.

Patent
26 Jan 2015
TL;DR: In this article, a method of controllably bonding a thin sheet having a thin-sheet bonding surface with a carrier having a carrier bonding surface was proposed, by depositing a carbonaceous surface modification layer onto at least one of the thin sheet bonding surface and the carrier's surface.
Abstract: A method of controllably bonding a thin sheet having a thin sheet bonding surface with a carrier having a carrier bonding surface, by depositing a carbonaceous surface modification layer onto at least one of the thin sheet bonding surface and the carrier bonding surface, incorporating polar groups with the surface modification layer, and then bonding the thin sheet bonding surface to the carrier bonding surface via the surface modification layer. The surface modification layer may include a bulk carbonaceous layer having a first polar group concentration and a surface layer having a second polar group concentration, wherein the second polar group concentration is higher than the first polar group concentration. The surface modification layer deposition and the treatment thereof may be performed by plasma polymerization techniques.

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the surface roughness and surface cleanness of Pyrex glass wafers by performing three renowned cleaning processes such as degreasing, piranha, and RCA 1&2 (SC‐Standard Cleaning 1 and 2).

Journal ArticleDOI
01 Sep 2015-Carbon
TL;DR: In this paper, a large area carbon nanotube field emission backlight was built with a new cathode structure, which involved unique gate insulator formation by glass etching, highly populated multi wall nanotubes tips, and gate electrode assembly by anodic bonding.

Patent
27 Jan 2015
TL;DR: In this article, a method of controllably bonding a thin sheet to a carrier was proposed, where the thin sheet has a thin-sheet bonding surface, and the carrier has a carrier bonding surface.
Abstract: A method of controllably bonding a thin sheet to a carrier, wherein the thin sheet has a thin sheet bonding surface, and the carrier has a carrier bonding surface. Depositing a surface modification layer onto at least one of the thin sheet bonding surface and the carrier bonding surface so as to obtain a first surface energy on the one of the thin sheet bonding surface and the carrier bonding surface. Then, treating the surface modification layer so as to change the first surface energy to a second surface energy, wherein the second surface energy is greater than the first. And bonding the thin sheet bonding surface to the carrier bonding surface via the surface modification layer. Depositing the surface modification layer, and treating it, may be done by plasma polymerization processes.

Journal ArticleDOI
TL;DR: In this paper, a diffractive optical element is fabricated in soda-lime float glass using a simple and inexpensive process, where the glass is sandwiched between a mesh anode (lattice constant 2 µm) and a flat metal cathode.
Abstract: A diffractive optical element is fabricated in soda-lime float glass using a simple and inexpensive process. The glass is sandwiched between a mesh anode (lattice constant 2 µm) and a flat metal cathode. Applying a direct current while at a moderately elevated temperature of 553 K induces thermal poling of the glass. The result is that the structured pattern of the electrode is imprinted on the glass as the electric field causes ion depleted regions where there is contact between the glass and electrode. The current-time dynamics of the structuring process along with X-ray element analysis and conductivity measurements are presented. Optical analyses of the resultant diffraction patterns of samples suggest that large-scale and complex patterns can be fabricated.

Journal ArticleDOI
21 Sep 2015-Sensors
TL;DR: The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S.
Abstract: This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the bonding parameters and their influence on bond interface properties and found that a phase transition from CuGa2 to Cu9Ga4 was primarily responsible for an increase in bonding strength.
Abstract: The low temperature joining of semiconductor substrates on wafer level by solid-liquid inter-diffusion bonding using the Cu/Ga and Au/In systems is investigated regarding the bonding parameters and their influence on bond interface properties. The focus is on temperature dependence and composition of interface. In the case of Cu/Ga bonding, a phase transition from CuGa2 to Cu9Ga4 was found to be primarily responsible for an increase in bonding strength. After the temperature treatment of 90°C, a shear strength of up to 90 MPa could be achieved. Furthermore, the combination of Au and In with composition ratios suitable for AuIn2 and AuIn intermetallic phase formation was investigated. In the case of AuIn shear strength, 96 MPa was achieved using a bonding temperature of 200°C. [2014-0325]

Proceedings ArticleDOI
26 May 2015
TL;DR: In this article, the authors reported the methodology of achieving low temperature, low pressure CMOS compatible Wafer-on-Wafer (WoW) Cu-Cu thermo-compression bonding using optimally chosen ultra-thin layer of Titanium (Ti) as a passivation layer.
Abstract: In this paper, we report the methodology of achieving low temperature, low pressure CMOS compatible Wafer-on-Wafer (WoW) Cu-Cu thermo-compression bonding using optimally chosen ultra-thin layer of Titanium (Ti) as a passivation layer. We systematically studied the effects of Ti thickness on bonding quality via its effects on surface roughness, oxidation prevention and inter diffusion of Cu. Through this study, we have found that a Ti thickness of 3 nm not only results in excellent bonding but also leads to a reduction in operating pressure to 2.5 bar and temperature to 175° C. The reduction in pressure is more than an order of magnitude lower relative to the current state-of-the-art. The lower operating pressure and temperature manifest themselves in a very good homogenous bond further highlighting the efficacy of our approach. Finally, our results have been corroborated by evidence from AFM study of the Cu/Ti surface prior to bonding. The bond strength of Cu-Cu as measured by Instron Microtester measurement system is found to be 190 MPa which compares very well with the reported literatures.