Showing papers on "Atomic layer deposition published in 1983"

Metal-silicide deposition using plasma-enhanced chemical vapor deposition

Abstract: A method for deposition of thin conductive layers of low resistivity titanium silicide. The method comprises the co-deposition of titanium and silicon by plasma-enhanced chemical vapor deposition at a low temperature. An anneal above the deposition temperature reduces the layer resistivity, making the layer especially suitable for microelectronic applications.

Chemical Vapor Deposition of PbTiO3Thin Film

Abstract: A PbTiO3 thin film has been grown on Pt or Pt-coated Si wafer by chemical vapor deposition instead of rf sputtering which makes a surface of substrate damaged. As the source material of the deposition, two kinds of combinations of (PbCl2 and TiCl4) and (PbO and Ti(C4H9O)4) have been tried to know the effect of chlorine inclusion in the PbTiO3 network. The surface of the film is much smoother than that of the film prepared by the rf sputtering, and deposition rate is several µm/hr. The deposited film structure is mostly oriented to or direction which depends on the source material and the deposition condition. The maximum dielectric constant of the film is 130, and D-E hysteresis characteristic has been also obtained.

How the ZnS:Mn layer thickness contributes to the performance of AC thin-film EL devices grown by atomic layer epitaxy (ALE)

Abstract: Luminance, efficiency, threshold voltage, and voltage polarity dependence of the light emission have been investigated as a function of the ZnS:Mn layer thickness in ac thin-film electroluminescent (TFEL) devices grown by Atomic Layer Epitaxy (ALE). The crystallinity of the ZnS:Mn layer was studied by X-ray diffraction. The layer of poor crystallinity is about 35 nm and coincides with the dead layer observed in luminance. Luminance is nearly proportional to the ZnS:Mn layer thickness and might indicate a homogeneous excitation throughout the layer at high voltages.

Thin Film Deposition Techniques

Abstract: As already pointed out in Chapter 1, a deposition technique and its associated process parameters have a characteristic effect on the nucleation- and growth-dominated microstructure of a thin film and thereby on its physical properties. Two-dimensional materials of thicknesses ranging from angstroms to hundreds of micrometers can be prepared by a host of so-called thin film as well as thick film techniques. The latter methods involve the preparation of thin materials from a paste or liquid form of the bulk material. The two sets of techniques yield thin film materials of widely different microstructures and properties.

Encroachment-Free Tungsten CVD Process for Self-Aligned Source-Drain-Gate Metallization

Abstract: Enhancement in integration density and performance of VLSIs has been achieved by scaling of MOSFETs' dimensions. However, the efforts to miniaturize MOSFETs will not profit us anything if the resistances of interconnects and contacts are not properly reduced. The scaling of junction depths and contact hole dimensions has resulted in increase in resistances of both source/drain and contacts, thus severely limiting the performance of scaled devices. Self-aligned silicidation technologies (1) have been introduced to overcome these difficulties. In these technologies, silicides are selectively formed on the surfaces of sources, drains and gates while the side walls of gates are protected from silicidation by-oxide spacers. The processes are successful in reducing resistances to 3-4 Q/ . However, further reduction in resistance by forming thicker silicide layers on very shallow junctions usually leads to junction failures, since silicide forming reactions proceed by consuming silicon atoms in the junction. An ideal scheme for eliminating parasitic resistances in scaled MOSFETs is the use of selective metal film deposition onto source, drain and gate surfaces instaed of forming silicide in the self-aligned process. However, in our earlier attempts, crucial difficulties were encountered, i.e., the gate to source/drain short or the failure of source/drain junctions were frequently observed. Such problems are the results of poor selectivity of tungsten deposition onto Si or SiO2 surface or the encroachment of tungsten that proceeds along the nearby SiSiO2 interface. The self-aligned meallization of source, drain and gate has been realized for the first time by employing the newly developed tungsten CVD process in which the deleterious encroachment phenomenon has been completely eliminated. It should be noted that our approach is different from the WOS technology (2) in which the metallization of source/ drain regions was not self-aligned to gate and an excess masking step was required. This paper describes the development of encroachment-free W-CVD process and its application to VLSI device fabrication. Figure 1(a) demonstrates the encroachment of W underneath the masking oxide, which extends about 2 pm. The nucleation and growth of W mounds on a SiO surface is shown in Fig. 1(b). In order io eliminate these problems, several improvements have been introduced in the W-CVD process. The chemical thermodynamics and mass transport theory have been extensively used for understanding the reactions in the process and for optimizing process conditions. We have found that the well-controlled two-step deposition is essential for realizing perfect deposition. An example of such perfect deposition is demonstrated in Fig. 1(c). In the first step, the following substitution reaction between WF and substrate Si is utilized:

A study of the compositional transition layer in In 1-x Ga x As y P 1-y inP heterojunction interface

Abstract: The atomic concentration of each composition of a thin quaternary layer grown by the two-phase supercooling LPE does not vary with the depth. The atomic concentration in the compositional transition layer versus the depth can be formulated as a hyperbolic tangent function which fits the experimental data very well.

Erosion and Transfer in Electrical Contacts Measured Using the Thin Layer Activation Technique

Abstract: The application of an ion beam activation technique to erosion studies in electrical contacts is demonstrated. The technique, which is based upon the labeling of a thin layer of surface atoms by high energy ion beam activation, is sensitive to both material loss from the activated layer and transfer to other components. As only a thin layer is activated the induced activity levels are low and the samples require only elementary radiological handling precautions. The information that can be obtained with the technique is demonstrated with the use of a readily available automobile contact rig incorporating tungsten contacts. Preliminary estimates of the erosion conditions are made, and the technique is then tailored to optimize experimental measurements. A typical measurement of material transfer between the two electrode faces was 50 ± 3 µg per 2 h of operation. An attempt to modify the properties of electrodes and hence their erosion rates by the ion implantation of silver ions is also reported.