Atomic layer deposition

About: Atomic layer deposition is a research topic. Over the lifetime, 19821 publications have been published within this topic receiving 477332 citations. The topic is also known as: ALD.

Large ferroelectric polarization of TiN/Hf0.5Zr0.5O2/TiN capacitors due to stress-induced crystallization at low thermal budget

Abstract: We report on atomic layer deposited Hf0.5Zr0.5O2 (HZO)-based capacitors which exhibit excellent ferroelectric (FE) characteristics featuring a large switching polarization (45 μC/cm2) and a low FE saturation voltage (∼1.5 V) as extracted from pulse write/read measurements. The large FE polarization in HZO is achieved by the formation of a non-centrosymmetric orthorhombic phase, which is enabled by the TiN top electrode (TE) having a thickness of at least 90 nm. The TiN films are deposited at room temperature and annealed at 400 °C in an inert environment for at least 1 min in a rapid thermal annealing system. The room-temperature deposited TiN TE acts as a tensile stressor on the HZO film during the annealing process. The stress-inducing TiN TE is shown to inhibit the formation of the monoclinic phase during HZO crystallization, forming an orthorhombic phase that generates a large FE polarization, even at low process temperatures.

Grain size engineering for ferroelectric Hf0.5Zr0.5O2 films by an insertion of Al2O3 interlayer

Abstract: The degradation of ferroelectric (FE) properties of atomic layer deposited Hf0.5Zr0.5O2 films with increasing thickness was mitigated by inserting 1 nm-thick Al2O3 interlayer at middle position of the thickness of the FE film. The large Pr of 10 μC/cm2, which is 11 times larger than that of single layer Hf0.5Zr0.5O2 film with equivalent thickness, was achieved from the films as thick as 40 nm. The Al2O3 interlayer could interrupt the continual growth of Hf0.5Zr0.5O2 films, and the resulting decrease of grain size prevented the formation of non-ferroelectric monoclinic phase. The Al2O3 interlayer also largely decreased the leakage current of the Hf0.5Zr0.5O2 films.

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as Gate Dielectric

Abstract: High-performance inversion-type enhancement-mode n-channel In053Ga047As MOSFETs with atomic-layer-deposited (ALD) Al2O3 as gate dielectric are demonstrated The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general A 05-mum gate-length MOSFET with an Al2O3 gate oxide thickness of 8 nm shows a gate leakage current less than 10-4 A/cm2 at 3-V gate bias, a threshold voltage of 025 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V The midgap interface trap density of regrown Al2O3 on In053Ga047As is ~14 x 1012/cm2 ldr eV which is determined by low-and high-frequency capacitance-voltage method The peak effective mobility is ~1100 cm2 / V ldr s from dc measurement, ~2200 cm2/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 05-10-MV/cm effective electric field

Periodic plasma annealing in an ALD-type process

Abstract: Methods for performing periodic plasma annealing during atomic layer deposition are provided along with structures produced by such methods. The methods include contacting a substrate with a vapor-phase pulse of a metal source chemical and one or more plasma-excited reducing species for a period of time. Periodically, the substrate is contacted with a vapor phase pulse of one or more plasma-excited reducing species for a longer period of time. The steps are repeated until a metal thin film of a desired thickness is formed over the substrate.

Atomic layer deposition of hafnium-based high-k dielectric

Abstract: A method of depositing a hafnium-based dielectric film is provided. The method comprises atomic layer deposition using ozone and one or more reactants comprising a hafnium precursor. A semiconductor device is also provided. The device comprises a substrate, a hafnium-based dielectric layer formed atop the substrate, and an interfacial layer formed between the substrate and the hafnium-based dielectric layer, wherein the interfacial layer comprises silicon dioxide and has a crystalline structure.