Showing papers on "Automatic test pattern generation published in 1972"

A New Approach to the Fault Location of Combinational Circuits

Abstract: A systematic approach to the location of a single failure in a combinational logic network is presented. The method utilizes only the required tests and needs no fault table. The structure of the logic network is taken into consideration when selecting the tests to be applied. For tree networks, we start from the gate that generates a primary output and sequentially trace back through the stages of the network according to a fixed set of rules. At each stage we either locate the fault or determine the direction of the trace.

Fault detection and localization in digital systems

Abstract: A method for synthesizing a test function which can detect and isolate a fault to the single input of a multiple input circuit and means for utilizing the resulting function is disclosed. The test circuit is a function only of the number of inputs to the circuit under test and not a function, as is the usual case, of what the circuit under test is performing.

Fault Identification in Electronic Circuits with the Aid of Bilinear Transformations

Abstract: A method has been developed for applying bilinear transformations to the identification of faulty components in linear electronic circuits. Simple magnitude and phase measurements, at a number of test frequencies, are made and plotted on a set of predetermined loci in the complex transfer-function plane. The data for plotting the loci are determined either experimentally or by circuit analysis with a digital computer. The faulty component and the parameter value are then determined from the loci. The method has the advantage that it provides a graphical representation of the circuit behavior with a faulty component and also readily allows experimental error to be taken into account when plotting the measured data. The method is demonstrated with a practical transistor amplifier circuit.

Statistical logic test system having a weighted random test pattern generator

Abstract: A system for testing complex circuitry primarily in large scale integration where a great number of inputs and outputs must be tested and the internal circuitry is inaccessible. The test system has a weighted random number generator which applies a test signal to some input terminals of the logic under test more frequently than others. A particular input terminal to the logic under test can be accessed in proportion to the circuit switching activity associated with accessing that particular terminal.

Fault simulation system for determining the testability of a non-linear integrated circuit by an electrical signal test pattern

Abstract: A system involving the use of fault simulation for determining whether a proposed non-linear integrated circuit is testable by a proposed incremental bilevel electrical signal test pattern. The system, which is particularly advantageous in determining the testability of integrated circuits having sequential logic, involves the conversion of the bilevel electrical test pattern into a corresponding three-level test pattern, and the application of said three-level pattern to a three-level "good" circuit simulation of the integrated circuit and to a number of three-level "bad" circuit simulations of said circuit, each of said "bad" circuit simulations being representative of a different stuck fault condition which is to be determined by the test pattern.

Secondary techniques for increasing fault coverage of fault detection test sequences for asynchronous sequential networks

Abstract: The generation of fault detection sequences for asynchronous sequential networks is considered here. Several techniques exist for the generation of fault detection sequences on combinational and clocked sequential networks. Although these techniques provide closed solutions for combinational and clocked networks, they meet with much less success when used as strategies on asynchronous networks. It is presently assumed that the general asynchronous problem defies closed solution. For this reason, a secondary procedure is presented here to facilitate increased fault coverage by a given fault detection test sequence. This procedure is successful on all types of logic networks but is, perhaps, most useful in the asynchronous case since this is the problem on which other techniques fail. The secondary procedure has been designed to improve the fault coverage accomplished by any fault detection sequence regardless of the origin of the sequence. The increased coverage is accomplished by a minimum amount of additional internal hardware and/or a minimum of additional package outputs. The procedure presented here will function as part of an overall digital fault detection system, which will be composed of: 1) a compatible digital logic simulator, 2) a set of fault detection sequence generators, 3) secondary procedures for increasing fault coverage, 4) procedures to allow for diagnosis to a variable level. This research is directed at presenting a complete solution to the problems involved with developing secondary procedures for increasing the fault coverage of fault detection sequences. iii