Showing papers on "Automatic test pattern generation published in 1976"

A Nine-Valued Circuit Model for Test Generation

Abstract: A nine-valued circuit model for test generation is introduced which takes care of multiple and repeated effects of a fault in sequential circuits. Using this model test sequences can be determined which allow multiple and repeated effects of faults on the internal state of a sequential circuit. Thus valid test sequences are derived where other known procedures, like the D-algorithm, do not find any test although one exists.

Transition Count Testing of Combinational Logic Circuits

Abstract: Logic circuits are usually tested by applying a sequence of input patterns S to the circuit under test and comparing the observed response sequence R bit by bit to the expected response Ro. The transition count (TC) of R, denoted c(R), is the number of times the signals forming R change value. In TC testing c(R) is recorded rather than R. A fault is detected if the observed TC c(R) differs from the correct TC c(Ro). This paper presents a formal analysis of TC testing. It is shown that the degree of detectability and distinguishability of faults obtainable by TC testing is less than that obtainable by conventional testing. t is argued that the TC tests should be constructed to maximize or minimize c(Ro). General methods are presented for constructing complete TC tests to detect both single and multiple stuck-line faults in combinational circuits. Optimal or near-optimal test sequences are derived for one-and two-level circuits. The use of TC testing for fault location is examined, and it is concluded that TC tests are relatively inefficient for this purpose.

Truth-Table Verification of an Iterative Logic Array

Abstract: This paper studies the problem of fault detection in iterative logic arrays (ILA's) made up of combinational cells arranged in a one-dimensional configuration with only one direction for signal propagation. It is assumed that a fault can change the behavior of the basic cell of the array in an arbitrary way, as long as the cell remains a combinational circuit. It is further assumed that any number of cells can be faulty at any time. In this way, testing an array is equivalent to verifying the correctness of its truth table. That could be done exhaustively through the application of a set of tests whose size is exponential in N, the number of cells in the array. The procedure presented in this paper generates a test set whose size is constant (i.e., independent of the number N of cells in the array). Conditions (on the structure of the basic cell) for the application of this procedure are presented. A practical example illustrating the application of this procedure is presented. Bounds for the size of the derived test set are presented and it is shown how to modify the basic cell of an arbitrary array in order to test it with a constant number of tests.

A Logic System for Fault Test Generation

Abstract: This paper describes a logic system specifically designed for fault test generation. The system allows the user to impose a set of initial constraints on the elements of a logic network by indicating those values which an element may (or may not) assume for the test under consideration. He can be as vague or as specific as he wants in imposing these constraints. A set of logic tables is then used to automatically propagate the effects of these constraints throughout the network. As a result of this logic propagtion, the necessary values of the elements in the network become much more precisely (if not completely) defined. The tables also indicate whether or not the generated test (which may include a number of unspecified values) is sufficient to detect the given fault. If several different tests will suffice, the choices remaining are clearly indicated. In the case of a redundant lead (untestable fault), propagation through the tables automatically results in a logical inconsistency.

About Random Fault Detection of Combinational Networks

Abstract: Fault detection by applying a random input sequence simultaneously to a network under test and to a reference network is conside-red. A distinction between testing quality and detection quality is given. The detection surface is introduced as a characteristic parameter of a combinational network. The results are applied to TTL combinational circuits.

Identification of Multiple Stuck-Type Faults in Combinational Networks

Abstract: This paper deals with the problem of identifying multiple stuck-type hardware failures in combinational switching networks. Our work is an extension of that of Poage, and Bossen and Hong, and we employ the cause-effect equation for representing faulty circuit behavior. We introduce the concept of solving simultaneous equations over check point variables. These check point solutions are studied in detail. From the solutions one can calculate the function realized by a faulty circuit. We outline an on-line testing procedure for constructing a test set for identifying a specific fault in a circuit to within an equivalence class. This procedure eliminates the need for precalculating a fault dictionary, which, in many instances, can be quite advantageous. We also outline how to apply these techniques to the following problems: 1) identifying redundancy; 2) determining the set of faults not detected by an arbitrary test set; and 3) constructing a complete fault dictionary.

A Module-Level Testing Approach for Combinational Networks

Abstract: A module-level testing approach for combinational networks which employs hardware modification and a simplified test generation procedure is described. The approach is based on a directed graph model for the network derived at the module level. The objectives of the approach are to deal with testing directly at the module level, to use cataloged tests for the modules in the network environment, and to generate a fault detection test set with "good" fault location capability. Networks which consist of single-output modules are treated initially and then the results are extended to networks which consist of multiple-output modules. Hardware modification and test generation procedures are illustrated.

Efficiency of Compact Testing for Sequential Circuits.

Abstract: : Compact testing uses random inputs to test digital circuits. Detection is achieved by comparison between some statistic property of the circuit under test, like the frequency of ones on the output line, and the same property for the fault-free circuit. This paper shows that compact testing can be used efficiently for sequential machines, although it has some inherent limitations. Synchronization is achieved by a long sequence of random inputs whose length is circuit dependent. However, for most sequential circuits, synchronization can be achieved in a few seconds. The great majority of failures inside the memory elements are easily detected even with short tests. Compact testing also detects most of the failures in the combinational parts. There, its efficiency is largely dependent upon the test length and also the characteristics of the random number generators. However, even the most subtle failures may be detected if the test has sufficient length. Some of the requirements and trade-offs to achieve efficient detection are presented.

Function test equipment for logical operation circuit

Abstract: PURPOSE: To obtain the logical operation circuit's function test equipment which makes it possible to test the input and output of the logical operation circuit having a two-way terminal. COPYRIGHT: (C)1978,JPO&Japio

An Integrated Circuit Fault Model for Digital Systems.

Abstract: : A model for the faulty behavior of digital networks realized using integrated circuit devices is proposed This model, the pin fault assumption, is based on a study of the most frequently encountered failure mechanisms for such networks, and the observation that previous fault assumptions model a large number of faults which occur with low frequency The basis for the pin fault model, and an investigation of multiple fault detection using this model are presented Fault detection for combinational modules is investigated, and it is shown that multiple pin fault detection test sets for such modules may be quite easily generated The computation required to generate such test sets is independent of the circuit realization internal to the model, and each test generated requires about the same amount of computation The computational complexity of test generation is greatly reduced compared to that for previously studied fault models Pin fault detection experiments for sequential machines are studied, and methods for designing such experiments are developed These design methods are compared to those under other fault assumptions, and a substantial reduction is observed in the length of such sequences and the computation required to produce them (Author)

A Programmable Fault Testing Equipment for Combinational Networks

Abstract: This paper deals with the design and construction of a fault-testing equipment. It can be used to test any type of permanent faults of stuck-at-type, whether single or multiple, in any irredundant combinational logic circuit with loop free interconnections. The inherent programming feature enables the system to test any arbitrary combinational network of any number of input variables with a maximum of eight and with an internal structure, made up with any arbitrary type of logic blocks. The presence or absence of any fault in the network under test is readily detected.