Showing papers on "Automatic test pattern generation published in 1977"

Test generation for large logic networks

Abstract: A system for automatic test pattern generation for large logic networks is described. The network to be tested is assumed to comply with a set of ground rules for testability. The system includes features for automatic subdivision of the network into easily tested sub-networks, automatic test generation programs, and a post-processor which produces a highly efficient test program. Applications to fault diagnosis, and to fast processing of design changes and variations for machine features are considered.

Simulator-oriented fault test generator

Abstract: The problem of generating tests for sequential logic networks has become severe with large-scale integration (LSI). Since the internal gates cannot be tested by direct measurements, it is imperative that a rigorous logic test be developed to ensure quality at the chip level. The sequential complexity of many LSI chips exceeds the practical limitations of the familiar technique of modeling sequential logic for the application of combinational logic test-generation algorithms. Although other approaches, such as pseudo-random pattern generation, have been tried with some success, the pattern count may be quite large. This paper describes a method of test pattern generation that was developed with three objectives: to generate long pattern sequences systematically when needed, to model the sequential logic accurately so that any test generated would be valid, and to focus on assumed faults such as stuck 1 and stuck 0. Also discussed are the strengths and limitations of this method and some comparative results.

SCIRTSS: A Search System for Sequential Circuit Test Sequences

Abstract: This paper describes SCIRTSS (a sequential circuit test search system). An analytical basis is given for using tree search techniques in determining test sequences for sequential circuits. The basic algorithm for the system of SCIRTSS programs is described and the extent to which the user can influence the search procedure is discussed. Included are the results of the application of SCIRTSS to eight sequential circuits of varying complexity on each one of which it succeeded in finding a fault detection sequence for at least 98 percent of the simple logical faults. This suggests that SCIRTSS can be effective on more complex LSI parts than other automatic test generation methods currently available. Breaking the tree search into two separate search procedures and partitioning circuits when possible into control and data sections are unique features which contribute to SCIRTSS efficiency.

An efficient method of fault simulation for digital circuits modeled from boolean gates and memories

Abstract: The ability to predict the behavior of digital circuits containing faults is required for the verification and automatic generation of fault detection tests, and for the creation of fault dictionaries. The most common method of prediction is with a fault simulation program.Fault simulators simulate the fault-free (good) circuit and each of the possible faulty circuits. In most cases, the faulty circuit is assumed to contain only a single fault modeled as either a component input or output stuck-at-0 (SA0) or stuck-at-1 (SA1). Even so, a typical circuit may imply hundreds to thousands of possible faulty circuits. Reducing the cost of simulating large numbers of faulty circuits is the first major consideration in fault simulation.

Fault Diagnosis of Semiconductor Random Access Memories.

Abstract: : This report deals with the problems of testing semiconductor random access memories and of locating faults on a memory board. Memory test procedures can be divided into three classes, functional testing, pattern sensitivity testing and DC parametric testing. Existing test procedures for testing semiconductor memories are either limited in their fault coverage or require a prohibitive amount of time. A new functional test procedure based on a fault model that takes into account a large variety of faults encountered with semiconductor memories is presented. The fault model is not based on the 'gate' level as in classical fault diagnosis but is formulated on a higher level in terms of functional blocks, like the decoder and the memory cell array. The proposed functional test procedure takes 0(n x log sub 2) units of time where n is the number of words in memory. This gives a dramatic improvement in the testing time required over well-known test procedures line 'galpat' and 'Walking Ones' which take 0(n squared) units of time. Algorithms for the functional test procedure are given. The problem of locating faults on a memory board to memory chips, decoder logic, data registers, and bussing structure is discussed. A test scheme for this problem is given. Finally various test procedures presented in the thesis are evaluated for fault coverage, time requirement and east of implementation.

Automatic test generation for large digital circuits

Abstract: This paper describes an implemented technique of automatic test generation for large digital circuits. The test generator presented in this paper basically uses the path sensitizing method and is applicable to all kinds of logical circuits. Some application results are also described.

Resolution-Oriented Fault Interrelationships in Combinational Logic Networks

Abstract: This correspondence considers fault resolution as a process of applying a sequence of input vectors, called tests, to a combinational logic network in order to resolve an existing fault situation from within a given master set of faults. A functional approach based upon an extension of the well-known Boolean difference concept to fault dependent situations is described. The test sets resulting from this extension, called fault dependent test sets, are fundamental to our considerations and are shown to be obtainable in a straightforward manner from standard test sets. Two fault interrelationships are defined which are particularly relevant to the resolution problem in that they algebraically describe the inherent limitations to the degree to which the existing fault situation can be resolved from within a given master set of faults using algebraic terminal experiments and fault dependent testing. Because these interrelationships are defined from a resolution-oriented point of view, they can be seen to be somewhat more intimate than other fault interrelationships which have been previously described in the literature. Some important ramifications of these interrelationships are discussed.

An advanced automatic test generation system for digital circuits

Abstract: : This is the third and final report documenting our research into the design of a new and powerful automatic test generation system for digital logic, called TEST/80. This system is designed around the following six concepts. 1. A powerful circuit preprocessing analysis which leads to greater efficiency during stimulus generation. 2. An effective initialization algorithm. 3. The use of time frames, phases and periods so that asynchronous circuits can be accurately processed during stimulus generation. 4. The use of functional level primitives so that complex circuits including shift registers, counters and RAM's, can now be effectively processed. 5. The use of a stimulus generation algorithm which incorporates the concepts in 1-4. 6. The use of a functional level concurrent fault simulator, used to grade a test and produce a fault dictionary.

Rapid fault finding tester for TV sets - has identical set as simulator with selective switching and indication of functional modules

Abstract: The fault-finding test jig for colour T.V. servicing comprises a fault simulator using an identical type of set to that under test. Each individual functional module (integrated circuit etc.) of the set under test is also fitted in the simulator (19-24). Each of these modules or groups of modules is wired to a selector and light-emitting diode mimic display panel (26, 27) associated with the control monitor (18). By selectively switching out, or by introduction of simulated fault signals, the fault on the test set can be reproduced on the simulator monitor screen. The light-diode matrix will then indicate on the simulator the module or group responsible for the faulty operation. It is then a simple matter to locate the fault in the set under test.