Showing papers on "Automatic test pattern generation published in 1979"

Fault diagnosis for linear systems via multifrequency measurements

Abstract: The fault diagnosis problem for a linear system whose transfer function matrix is measured at a discrete set of frequencies is formalized. A measure of solvability for the resultant equations and a measure of testability for the unit under test is developed. These, in turn, are used as the basis of algorithms for choosing test points and test frequencies.

Detection of Faults in Programmable Logic Arrays

Abstract: A new fault model is proposed for the purpose of testing programmable logic arrays. It is shown that a test set for all detectable modeled faults detects a wide variety of other faults. A test generation method for single faults is then outlined. Included is a bound on the size of test sets which indicates that test sets are much smaller than would be required by exhaustive testing. Finally, it is shown that many interesting classes of multiple faults are also detected by the test sets.

Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)

Abstract: Programmable logic arrays (PLA's) are the logic implementation vehicle for many applications. Due to their regular structure, one is able to model and analyze many more of the likely physical faults than the conventional stuck faults considered for random combinational logic implementations. We investigate shorts between the lines and crosspoint defects (spurious absence or presence), as well as stuck faults in a PLA. It is shown that a complete crosspoint test set also detects most of all faults analyzed. The crosspoint-oriented test set is compact, easy to generate, and technology-invariant. For the test generation, the regularity of the PLA structure is utilized for ease of computation and for test set optimality. Groups of crosspoint defects are sensitized simultaneously. For each such fault group, a test configuration which contains the totality of the tests for the faults under consideration is efficiently generated. When the configuration is empty, there exists no test that detects the particular group of faults. A covering set of tests is then selected from the configuration. Our test generation method (TPLA) uses two basic and effective heuristics; they are the initial word ordering for processing and the use of look-ahead merit function whenever there is a free choice of values in a test input variables.

Testing Logic Networks and Designing for Testability

Abstract: VLSI has brought exciting increases in circuit density and performance capability. But it has also aggravated the problem of chip, component and system testing. Here are some approaches to dealing with that problem.

Fault dictionary based upon stimulus design

Abstract: A method of fault signature generation is presented that is based upon state space analysis of linear circults. An input control sequence is designed to reduce a nontrivial initial state of the circuit under test to the zero state in finite time. The realization of this stimulus as a piecewise constant waveform has step amplitudes that are exponential functions of the poles of the circuit under test. Perturbations of these amplitudes, engendered by element drift failure, constitute a fault signature. Single element value perturbations engender fault signature trajectories in signal space, and the fault dictionary is constructed by defining disjoint decision regions (hypervolumes) around each fault signature trajectory in the signal space. Circuit zeros of transmission allow the dimension of the signal space to be augmented with perturbation of such response waveform parameters as zero crossings. The theory of stimulus design for fault isolation in linear networks and a generalized matrix inverse method for computing the stimulus amplitudes from the pulse response of strictly proper circuits are presented. Examples of response waveforms and fault signature trajectories are given for several circuits.

Simplified ATPG and analog fault location via a clustering and separability technique

Abstract: Automatic test program generation (ATPG) for analog system fault location is considered and a procedure for generating a set of tests for a linear network using gain and phase measurements from input-output measurements only is presented. The best subset of features for fault diagnosis is selected via a discriminatory index. Each feature subset selected during the optimization procedure is tested for enhanced separability of observation space for faults and the efficiency of the subset for diagnosis is indexed using a confidence level. The fault matrix formed using the selected feature subset is analized for cluster formation, the separability measure introduced is used to group the fault cases and a reduction of the cases to be considered on-line is obtained. In fault location, a fault is identified to a specific group which then is further located to the individual component and is carried out for varying production tolerances.

Fault isolation algorithm for analog electronic systems using the fuzzy concept

Abstract: We are mainly concerned with enhancing ATPG for analog nonlinear circuits. For simplicity we are dealing only with the isolation of single fault cases. Due to the imprecision and indeterminacy of the complex structure of faulty networks, it is usually difficult to obtain exact solutions. Furthermore, for fault isolation it is often unnecessary to seek the exact solutions. In fact we find it useful to treat such faulty networks as fuzzy systems. The algorithm presented herein makes use of the available measured data on port responses to isolate the faulty components based on fuzzy set concepts. An illustrative example using the NAP2 network analysis program is included. These results aie compared with previous results based on other criteria.

Multiple Fault Diagnosis in Combinational Networks

Abstract: The concept of prime faults is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a structurally equivalent fault with prime faults as its only components. Functional and structural masking and covering relations among faults are defined. These relations can be exploited to greatly simplify multiple fault analysis and their test generation. We present an efficient algorithm that generates a multiple fault detection test set and identifies redundancies. Suggestions for designing networks to yield a minimum number of tests in the multiple fault detection test set are also included.

On Necessary and Sufficient Conditions for Multiple Fault Undetectability

Abstract: This correspondence states necessary and sufficient conditions for a multiple stuck-at fault in a combinational network to be undetected by a test set. The conditions are given in terms of fault masking relationships. It is shown that several other statements on this subject which have appeared in the literature are invalid.

Behavioral-Level Test Development

Abstract: An argument is made that the economics of test development in the LSI-VLSI era require creation and use of test development software aids that operate from high-level behavioral circuit models. Behavioral models are defined to be abstract specifications of the circuit function. Problems with the use of current-day gate-level software aids are discussed. Suggestions are given for implementing behavioral-level test generation tools. Recent work in this area at Texas Instruments Incorporated (TI) is discussed.

Systematic fault simulation in an analog circuit simulator

Abstract: With the recent increase in both fault isolation and fault tolerant design, automated and systematic methods of analyzing fault situations and their impact on the operation of solid-state circuitry are becoming increasingly important. In this paper we will explore the philosophy and techniques behind the design of a system for simulating various catastrophic failures in integrated circuits which is being implemented in a commercially available nodal circuit simulator ISPICE. We address the issues of how certain failure conditions can be identified and simulated, how certain sets of such conditions can be identified and used to reduce the cost of such a simulation without impacting the results, and how well structured reports can reduce large volumes of data to easily interpreted results. Finally, we also explore some of the more elaborate analysis and reporting techniques we expect to include in future implementations of automated fault diagnosis software.

Generation of software for computer controlled test equipment for testing analog circuits

Abstract: The NOPAL system automatically generates programs in the ATLAS test programming language to test and diagnose malfunctions in analog electronic circuit boards. The system consists of two parts: a top part which analyzes the circuit diagram and determines the necessary tests, and a bottom part which analyzes the required tests and produces a program in the RCA EQUATE ATLAS test language for use with the RCA AN/USM-410 automatic test equipment. The top part, the NOPAL language, and the bottom part are described in respective sections of the article. The operation and advantages of NOPAL are also illustrated with an example of a voltage regulator circuit board. The article concludes with a discussion of features of NOPAL for generating programs in other test programming languages and for other automatic test equipment.

A pragmatic approach to automatic test generation and failure isolation of analog systems

Abstract: Digital automatic test generation has been successful due to simplified modeling at the logic gate or higher level, rather than the component level, and to logic simulation performed for the stuck-at failure mode only. Analog automatic test generation generally requires modeling and simulation at the component level and continuous failure modes over a certain range of parameter values. As a result, most analog automatic test generation and fault isolation techniques demand a large computational capability on the ATE or off-line computers. Any practical analog automatic test generation solution must eventually address this problem. All analog automatic test generation techniques presently under investigation assume the availability of all or certain designated nodes as test points for stimulus injection and/or response measurement. This assumption suggests the possibility of GO-NO-GO tests to fault isolate to a "primitive," which may contain several circuit components. The "complementary signal" design suggested by Schrelher, appears well suited for providing an effective GO-NO-GO test; the signal and its response are determined by the poles and zeros of the circuit.

A Functional Form Approach to Test Set Coverage in Tree Networks

Abstract: To efficiently perform the fault analysis of digital networks it is necessary that pertinent fault interrelationships be utilized. However, to determine these fault interrelationships can entail an analysis which is quite complex and thereby reduces the overall advantage of utilizing the gained insights in a fault analysis process. In this paper we suggest an approach to establishing the existence of a certain fault interrelationship relative to test set coverage in tree networks which is based only on the form of the output function. A procedure is given for generating a form expression (called an L-expression) corresponding to that function. A theorem is stated regarding the interpretation of these form expressions relative to test set coverage.

On the use of procedural models for generation of test programs

Abstract: An approach based on artificial intelligence concepts is developed for automatic generation of test programs for analog circuits. The programs will, with the help of automatic test equipment (ATE), make appropriate measurements and deduce the location of potential faults in analog circuit boards.

Test system for logic unit

Abstract: PURPOSE: To make easy the test of print board unit mounting complicated LSIs and to reduce the cost and time, by mounting a dummy logic circuit unit and performing a simulation test from the input and output terminal of logic unit. CONSTITUTION: Considering that the adequacy of the entire print board unit 1 can practically and sufficiently be guaranteed (except the adequacy of LSI4 already proved) when only the adequacy of the peripheral circuits except LSI4 can be tested, the dummy circuit 4' having required and sufficient function only in testing the peripheral circuit is formed, it is mounted in place of the LSI4 for the test of the unit 1. The test data for the peripheral circuit assembling the circuit 4' can considerably be simplified in comparison with the test data for the circuit including LSI4 and sufficient test rate can be obtained. COPYRIGHT: (C)1980,JPO&Japio

Automatic test generation for LSI chips and printed circuit boards

Abstract: This paper will describe automatic test pattern generation methods and results for level sensitive scan design chips and boards, suitable for LSI networks.

Comments on "Multiple Fault Detection in Combinational Network"

Abstract: In the above paper,1the authors have defined complete test, closed fault set, fault set graph, and undetected fault set as follows.