Showing papers on "Automatic test pattern generation published in 1980"

Test Generation for Microprocessors

Abstract: The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by the availability of a large variety of microprocessors which differ widely in their organization, instruction repertoire, addressing modes, data storage, and manipulation facilities, etc. In this paper, a general graph-theoretic model is developed at the register transfer level. Any microprocessor can be easily modeled using information only about its instruction set and the functions performed. This information is readily available in the user's manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model. Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described.

Syndrome-Testable Design of Combinational Circuits

Abstract: Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size.

An Experimental Delay Test Generator for LSI Logic

Abstract: Delay testing is a test procedure to verify the timing performance of manufactured logic networks. When a level-sensitive scan design (LSSD) discipline is used, all networks are combinational. Appropriate test patterns are selected on the basis of certain theoretical criteria. These criteria are embodied in an experimental test generation program. The program has successfully produced sets of delay tests for large logic networks. The average coverage achieved by these tests faDs within 95.8 percent to 99.9 percent of optimal.

Test Generation Costs Analysis and Projections

Abstract: Empirical observations are used to derive analytic formulae for test volumes, parallel fault simulation costs, deductive fault simulation costs, and minimum test pattern generation costs for LSSD logic structures. The formulae are significant in projecting growth trends for test volumes and various test generation costs with increasing gate count G. Empirical data is presented to support the thesis that test volume grows linearly with G for LSSD structures that cannot be partitioned into disjoint substructures. Such LSSD structures are referred to as "coupled" structures. Based on empirical observation that the number of latches in an LSSD logic structure is proportional to the gate count G, it is shown that the logic test time for coupled structures grows as G/sup 2/. It is also shown that (i) parallel fault simulation costs grow as G/sup 3/ (ii) deductive fault simulation costs grow as G/sup 2/, and (iii) the minimum test pattern generation costs grow as G/sup 2/. Based on these projections some future testing problems become apparent.

Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis

Abstract: In this paper we present a new approach to multiple fault diagnosis in combinational circuits based on an effect-cause analysis. The main vehicle of our approach is the deduction of internal line values in a circuit under test N*. The knowledge of these values allows us to identify fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). A fault situation specifies faulty as well as fault-free lines. Other applications include identifying the existence of nonstuck faults in N* and determination of faults not detected by a given test, including redundant faults. The latter application allows for the generation of tests for multiple faults without performing fault enumeration.

Functional Level Primitives in Test Generation

Abstract: This paper deals with the use and development of high-level (functional) primitive logic elements for use in a system which automatically generates tests for complex sequential circuits. The concept of solution sequences to test problems for primitive elements is introduced and a functional language used to describe solution sequences is presented. Functional test generation models for two basic elements, a shift register and a counter, are derived, including procedures for implication, D-drive and line justification. Primitive algorithms which generate single as well as multivector (sequences) solutions to D-drive and line justification problems are presented.

Testability Considerotions in Microprocessor-Based Design

Abstract: Microprocessors are difficult to test–many failure modes exist and access to internal components is limited. Design techniques that enhance testability can reduce the impact of these constraints.

Digital Test Generation and Design for Testability

Abstract: This paper is a tutorial intended primarily for individuals just getting started in digital testing. Basic concepts of testing are described, and the steps in the test development process are discussed. A pragmatic approach to test sequence generation is presented, oriented towards ICs interconnected on a board. Finally, design for testability techniques are described, with an emphasis on solving problems that appeared during the test generation discussion.

Test Generation Techniques

Abstract: Existing test generation procedures are rooted in the SSI/MSI era. New techniques will cope with today's vastly more complicated LSI/VLSI systems.

An Objective Printed Circuit Board Testability Design Guide and Rating System.

Abstract: : A methodology was developed during this study that accurately evaluates the testability merits of a printed circuit board (PCB). This is accomplished through a 'Figure of Merit' rating system that weighs the 'difficult to test' and 'easy to test' aspects of a circuit design. The principal output of this study is an extensive Testability Design Guide that describes how testability problems associated with circuit structure can be corrected. The Design Guide works hand-in-hand with the rating system, such that the rating system identifies the nature and extent of the current testability problem and the guide provides the means to correct the design deficiencies. The developed guide and evaluation procedures were demonstrated on a number of 'difficult to test' PCBs which resulted in much improved fault isolation and significantly reduced times. (Author)

An Optimized ATPG

Abstract: This paper describes a hierarchical approach to the detection of the critical faults of a digital board, i.e., those most likely to occur. The failure probabilities of the nodes of a board are estimated and used as weights in selecting the nodes for fault detection. The study has indicated both a saving in pattern generation and a higher fault detection per pattern. This approach introduces a new definition of fault coverage. The approach is also applicable to analog circuits. In addition, it allows for continual incorporation of field data, thus improving the estimation of the failure probabilities.

Test Generation and Fault Isolation for Microprocessors and Their Support Devices.

Abstract: : This report covers the generation of tests for complex digital devices, implementation of those tests on currently available ATE, and fault isolation. Techniques are described for the modeling of devices in order to facilitate the testing process. A new algorithm for fault dictionary searching is given. Voltage Contrast (on the Scanning Electron Microscope) was used as an aid for fault insertion, which in turn provided test cases for fault isolation. Computer-Aided Test techniques are described. As the demonstration vehicle for this work was the development of MIL-M-38510 Detail Specifications (Slash Sheets) a tutorial description of a recommended slash sheet format is given. Many areas were only touched on during this contract; these have been described, with suggestions for further research topics. (Author)

A New Test Pattern Generation System

Abstract: This paper discusses the main shortcomings of existing software test pattern generation systems and describes the development of a new system. The new system will be developed in two phases. The first phase is called the scan-in/scan-out test generation sub-system. This sub-system will be used for testing designs which have 100% scan-in/scan-out (reading or writing of every register from external world is possible). The second phase will include the development of efficient general functional models. The test generation system to be developed in the first phase will be updated to incorporate the capability of handling such models. The functional models include general-combinational, register, counter, ROM, RAM, and microprocessor. In this paper, only, an outline of some of the distinct features of the system will be described.

A Remark on the Nonminimality of Certain Multiple Fault Detection Algorithms

Abstract: Poage has constructed a complex fault detection algorithm which generates a complete and minimal test set of all multiple stuck-at faults of a given combinational network. Several authors have derived from his method fast and simple multiple fault detection algorithms, which are claimed to generate complete test sets with a "near-minimal" or "near-optimal" number of tests. We show that the algorithms by Bossen and Hong and the algorithm by Yang and Yau may generate test sets with an exponential number of tests (relative to the number of inputs) where a linear number of tests is sufficient for a complete multiple fault detection test set.

Fault detection in combinational circuits using a compressed fault table

Abstract: A method is developed for obtaining a highly compressed fault table for two-level combinational circuits. A set of operations is defined through which the minimal test set for detecting stuck-at faults is obtained from the compressed fault table. The method is equally suitable for sum of products form or product of sums form realization of logic functions and generates the test set directly from the algebraic expression of the logic function.