Showing papers on "Automatic test pattern generation published in 1982"

Integrated circuit test apparatus test head

Abstract: An improved test system for performing DC and AC parametric and dynamic functional testing of multi-terminal integrated circuits is described. All of the circuitry for producing and responding to D.C. and high-integrity stimulus and response test signals is located within a Test Head module sized for use in close proximity of the device under test. A high-integrity bus in the Test Head interconnects the high-integrity producing and handling circuits, with inexpensive connectors and batch-fabricated printed circuit board techniques. A Controller provides digital test commands for energizing the test signal producing cirucits within the Test Head and for evaluating the test results. The control and measurement signals passing between the Controller and the Test Module require no special conductor implementation techniques. A unique detachable, modularized bussing scheme between the Controller and Test Head and within the Test Head enables the test system to be manufactured at minimum cost, while maximizing reliability, signal integrity and manufacturing repeatability from system to system and enables rapid replacement and interchangability of test circuits and functional capabilities without sacrificing the quality of bus structure that carries the high integrity signals.

Verification Testing

Abstract: A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present-day automatic test pattern generation (ATPG) programs. Fault simulation is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher - all irredundant multiple as well as single stuck faults are detected. Test length is easily controlled. The test patterns are easily generated algorithmically either by program or hardware.

Test circuit for turn-on and turn-off delay measurements

Abstract: A test circuit that is particularly suitable for inclusion on an LSI chip when testing a new technology or process. The circuit will enable accurate determination of the effects of loading on the turn-on and turn-off delays of one or more logic circuits on the chip. These determinations are based upon a comparison of the periods of different signals obtainable from the test circuit.

Fault detection test generation at the register transfer design level

Abstract: The authors describe the continuing development of a program capable of automatic generation of sequences of inputs for detection of faults in VLSI digital networks. The only description of a digital system required by the program is written in the hardware description language, AHPL (a hardware programming language). Together with a function level simulator and a hardware compiler the test generation program called SCIRTSS (sequential circuit test search system) form the front end of a design automation process. 10 references.