Showing papers on "Automatic test pattern generation published in 1983"

Universal testing circuit and method

Abstract: A test circuit, called a universal testing block (UTB) for on-chip testing of a VLSI subsystem such as a ROM or an ALU has several modes, including test generator and test evaluator, formed on the VLSI chip. The test generator circuit includes means for applying a predetermined test pattern to an input channel of the subsystem and may be a generator for generating pseudorandom test patterns for application to the subsystem. Alternatively, the test generator may be a counter which can be selectively activated to generate a binary up-count. The UTB also has a shift register mode having a serial input and output to enable serial data to be shifted into and out of the subsystem in parallel fashion. The test evaluator circuit receives output signals from the subsystem, and includes a parallel signature analyzer to generate a signature of the subsystem after the application of the test patterns by the input circuit to indicate whether the subsystem is fault-free. Also, means are provided for evaluating the signature and for generating a signal in accordance with the evaluation indicative of whether the subsystem is fault-free.

Test-generation system for digital circuits

Abstract: In a system for generating tests for digital circuits, a fault simulator (16) simulates a fault-free version of the circuit and all expected faulty versions of it concurrently, basing its operation on information contained in a data base (12) that contains information about the structure and possible defects of the circuits to be tested. A waveform system (14) carries high-level information regarding the general structure of the test waveform that ultimately is to be derived, such as clock signals, timing constraints, and other restrictions that the designer of the circuit under test has placed on the signals to be applied to it. At each point in this outline waveform at which the system needs to insert input signals, a test generator (18) is called by the waveform system (14) to derive a test vector based on information concerning the layout of the circuit, its possible defects, and its current state, the current state having been communicated to the data base (12) by the fault simulator (16), which determines the states that result from application of a waveform received from the waveform system (14). Even for non-scan-type circuits under test, the test generator derives only one test vector at a time, without searching through sequences of test vectors to find which sequences of test vectors might cause propagation of faults to the output ports of the circuit under test. It nonetheless efficiently derives test waveforms because it chooses among the fault effects of all faulty versions of the circuit concurrently for those effects that are likely candidates for propagation.

Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals

Abstract: This paper describes a program which generates test patterns for scan design circuits with tri-state modules and bidirectional terminals. The test generation procedure uses a path sensitization technique with 14 signal values. The principal features of this program are test generation with automatic decision of I/O mode of bidirectional terminals, generation of test sets for high impedance state, and generation of test sets for system clock control circuits of shift register latches (SRLs) by using shift-in function of SRLs.

LSI Testing Techniques

Abstract: Tests good for SSI and MSI circuits can't cope with the complexity of LSI. New techniques for test generation and response evaluation are required.

Quality Level and Fault Coverage for Multichip Modules

Abstract: A relationship between the quality level of a multichip module package and test coverage is established. A fault model for each stage of assembly of the package is assumed and the contribution of each of these stages to the quality level is assessed to produce the required relationship to test coverage achieved through test generation programs.

An Automatic Test Set for the Dynamic Characterization of A/D Converters

Abstract: An automatic test set is described for measuring the dynamic characteristics of A/D converters having up to 16 bits of resolution. The test converter is exercised with stepped input changes typical of the conditions of actual use. All dynamic test parameters are under program control, making it possible to separate and measure dynamic errors of various sources. Typical test results are included.

Multi-chip module test and diagnostic methodology

Abstract: The development of a manufacturing test and diagnostic methodology for multi-chip modules as used in the IBM 4300 processor models involves determining the most attractive compromise among a number of conflicting factors: a) high test coverage, b) high diagnostic resolution, c) test generation, d) test equipment, and e) test application and diagnosis. This paper describes a set of solutions which were developed to create a high-volume, low-cost manufacturing test operation for the product in question. This paper examines the role of the testing methodology in productivity and product quality, details the diagnostic approach chosen, and provides an example of the overall manufacturing system performance achieved by analyzing a large module production sample.

Design for testability.

Abstract: Testing of circuits with a few hundred logic functions can, in general be performed by the use of selected logic stimuli (Mueldorf and Savkav (1)). Exhaustive testing of circuits demands that all possible logic states in which a circuit can exist must be considered. Automatic test pattern generation (ATPG) methods (Williams and Parker (2), Papaionnou (3), Schnurmann et al (4)) can be used to effect in determining the test stimuli (or test vectors) required to achieve or approximate such an exhaustive test. For combinational circuits where the present states of the output variables are a function only of the present states of the input variables, exhaustive testing requires derivation of a test sequence to create all of the possible input combinations and check the outputs for correct responses. These input stimuli can be applied from automatic test equipment systems (ATE) and the responses can subsequently be sensed by the same equipment.

Fault diagnosis of bit-slice processor

Abstract: This paper proposes a microdiagnostic procedure for efficient fault diagnosis of bit-slice processors that are formed by an array of identical bit-slice processors. A test generation procedure for testing the entire array simultaneously instead of testing single slice, one after another, is presented, which is based on the high functional fault model and restricted multiple slice fault assumption within an array. Fault detection and fault location procedures using the generated test sequence are also presented. Using these procedures, a test microprogram and diagnostic system for the bit-sliced processor constructed by the array of four Am 2901 bit-slices are developed.