Showing papers on "Automatic test pattern generation published in 1984"

Random Pattern Testability

Abstract: A major problem in self testing with random inputs is verification of the test quality, i.e., the computation of the fault coverage. The brute-force approach of using full-fault simulation does not seem attractive because of the logic structure volume, and the CPU time encountered. A new approach is therefore necessary. This paper describes a new analytical method of computing the fault coverage that is fast compared with simulation. If the fault coverage falls below a certain threshold, it is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault coverage of the random test.

Verification Testing—A Pseudoexhaustive Test Technique

Abstract: A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present day automatic test pattern generation (ATPG) programs. Fault simulation or fault modeling is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected. The test patterns are easily generated algorithmically either by program or hardware.

Synchronization and Specification Issues in Protocol Testing

Abstract: Protocol testing for the purpose of certifying the implementation's adherence to the protocol specification can be done with a test architecture consisting of remote tester and local responder processes generating specific input stimuli, called test sequences, and observing the output produced by the implementation under test. It is possible to adapt test sequence generation techniques for finite state machines, such as transition tour, characterization, and checking sequence methods, to generate test sequences for protocols specified as incomplete finite state machines. For certain test sequences, the tester or responder processes are forced to consider the timing of an interaction in which they have not taken part; these test sequences are called nonsynchronizable. The three test sequence generation algorithms are modified to obtain synchronizable test sequences. The checking of a given protocol for intrinsic synchronization problems is also discussed. Complexities of synchronizable test sequence generation algorithms are given and complete testing of a protocol is shown to be infeasible. To extend the applicability of the characterization and checking sequences, different methods are proposed to enhance the protocol specifications: special test input interactions are defined and a methodology is developed to complete the protocol specifications.

Applications of testability analysis: from ATPG to critical delay path tracing

Abstract: This contribution outlines the applications of a recently proposed testability analysis algorithm that has been implemented as a controllability/ observability program named COP. Several benchmark modules, some approaching the complexity of VLSI, established that CPU cost grows only linearly with the size of the modules in all of the applications considered to date. These include effective heuristics for automatic test pattern generation (ATPG), assessment of random pattern testability, effective approach to approximate fault simulation. structural partitioning into cones, critical delay path tracing and characterization of the module in terms of a "testability signature". In view of the increasing complexity of VLSI, such performance provides strong motivation that the calibration of testability analysis be enhanced and its role further expanded.

LOCST: A Built-In Self-Test Technique

Abstract: A built-in self-test technique utilizing on-chip pseudorandom-pattern generation, on-chip signature analysis, a ``boundary scan'' feature, and an on-chip monitor test controller has been implemented on three VLSI chips by the IBM Federal Systems Division. This method (designated LSSD on-chip self-test, or LOCST) uses existing level-sensitive scan design strings to serially scan random test patterns to the chip's combinational logic and to collect test results. On-chip pseudorandom-pattern generation and signature analysis compression are provided via existing latches, which are configured into linear-feedback shift registers during the self-test operation. The LOCST technique is controlled through the on-chip monitor, IBM FSD's standard VLSI test interface/controller. Boundary scan latches are provided on all primary inputs and primary outputs to maximize self-test effectiveness and to facilitate chip I/O testing. Stuck-fault simulation using statistical fault analysis was used to evaluate test coverage effectiveness. Total test coverage values of 81.5, 85.3, and 88.6 percent were achieved for the three chips with less than 5000 random-pattern sequences. Outstanding test coverage (≫97%) was achieved for the interior logic of the chips. The advantages of this technique, namely very low hardware overhead cost (≪2%), design-independent implementation, and effective static testing, make LOCST an attractive and powerful technique.

Design of test pattern generators for built-in test

Abstract: This paper presents methods for designing cost-effective on-chip built-in test generators. Given an unordered test set, these methods produce an area and time efficient generator circuit using a small ROM and some additional logic. Some simulation results are presented.

Built-in test for CMOS circuits

Abstract: In CMOS technology combinational circuits become sequential in the presence of stuck-open faults. Instead of a single test pattern a sequence of patterns is necessary for each such fault. In this paper two kinds of hardware test generation techniques for built-in testing are described which produce the required sequences. One approach is suitable for sequential CMOS circuits the other for combinational CMOS circuits.

Hitest: A Knowledge-Based Test Generation System

Abstract: Efforts to develop computer-based automatic test generation for digital circuits have been generally unsuccessful, except in the case of combinational circuitry. Current ATPG methods for sequential circuits often require a considerable amount of computer time and generate unstructured test waveforms of limited value. Experienced human test programmers, on the other hand, appear to have little difficulty in generating high-quality tests for complex sequential circuits when they have a good understanding of how the circuit operates. This article considers the causes of failure in automatic test generation algorithms and describes a new system called Hitest. This system lets the computer use human understanding of circuit operations to generate more effective tests.

Fault Modeling for Digital MOS Integrated Circuits

Abstract: A new fault modeling technique aimed at efficient simulation and test generation for complex digital MOS IC's is described. It is based on connector-switch-attenuator (CSA) analysis, which employs purely digital models of switching transistors, resistive/capacitive elements, and their associated signals. The use of CSA networks to model the digital behavior, both static and dynamic, of MOS circuits is reviewed. It is shown that most physical failure modes in such circuits, including short-circuit, open-circuit, and delay faults, can be modeled more efficiently by CSA models than by conventional approaches. A generalized single stuck-line (GSSL) fault model is suggested as a uniform and practical method for fault representation.

On a theory of t-fault diagnosable analog systems

Abstract: The theory of t -fault diagnosable systems initiated by Preparata et al. has been studied for applications to automatic self-testing of large scale digital systems. Recently, Amin introduced another variation of their model. In this paper, we show that this model has an application to analog fault diagnosis. We further specialize Amin's model to obtain characterization theorems which are much more transparent and also are more suitable for this particular application.

An analysis of the multiple fault detection capabilities of single stuck-at fault test sets

Abstract: Multiple fault detection using single stuck-at fault test sets is considered. The 74LS181 4-bit ALU is analyzed using 10 test sets varying widely in length and method of generation. The simulation results demonstrate significantly higher multiple fault coverage than anticipated by previous studies. It is shown that single stuck-at fault test sets can provide suitably high fault coverage for practical circuits with multiple outputs and reconvergent internal fanout.

Circuit tester having on-the-fly comparison of actual and expected signals on test pins and improved homing capability

Abstract: A circuit tester and test technique are presented that compresses the amount of data stored in local test data RAMs for the implementation of a circuit test, thereby reducing the amount of data that must be downloaded to the local test data RAMs, thereby improving test throughput. Derivative data vectors are utilized in addition to raw data vectors as part of the data compression technique. Further compression results from storing only unique data vectors in the local test data RAMs and utilizing a sequencer to control the order in which the unique data vectors are utilized. The sequencer includes test program logic and logic capable of implementing on test pins indirect counters.

The inadequacy of the stuck-at fault model for testing mos lsi circuits: a review of mos failure mechanisms and some implications for computer-aided design and test of mos lsi circuits

Abstract: The stuck-at fault model is widely used as the basis for automatic test pattern generation in digital circuit testing, for example the D-algorithm. However, there have been growing doubts over the ability of the model to cover faults that occur in MOS LSI circuits. The paper consists of a review of the failure mechanisms that produce faults in MOS LSI circuits, a discussion of the problems that arise when using the stuck-at fault model to test MOS LSI circuits and a set of guidelines for the future development of computer-aided design and test of such circuits.

Test generation for MOS circuits

Abstract: Test generation for transistor switch faults is considered for nMOS combinational circuits. Examination of fault effects shows that memory and non-digital signals can result. A test strategy that accounts for MOS physical properties such as charge storage and bidirectionality is developed. Abstraction of physical effects using ternary algebra can guarantee the generation of valid tests.

Design for Testability for Complete Test Coverage

Abstract: Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achieve. This article presents DFT methods aimed at achieving total coverage. Two methods are compared: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation. The other method employs a test pattern generation algorithm (the FAN algorithm). Results show that 100 percent coverage within the allowed limits is difficult with the former approach. The latter, however, enables us to generate a test pattern for any detectable fault within the allowed time limits, and 100 percent test coverage is possible.

Taking into Account Asynchronous Signals in Functional Test of Complex Circuits

Abstract: The proposed functional test method for complex circuits presents the following features:- the test problem is studied in the aggregate; a test method, a test environment and automated test program generation are proposed.- the circuit behavior is considered as a whole. including the response to instructions (or commands). and to signals at the same level.Emphasis is put on the signal test: an hardware which allows the test of signals and is compatible with functional testing is defined; a description language for signal timing diagrams is proposed.

ATWIG, an automatic test pattern generator with inherent guidance

Abstract: ATWIG is a heuristic automatic test pattern generator (ATG) which employs various types of guidance based on controllability and observability (C/O) measures and various heuristics fault' path and fault selection. Guided inconsistent path sensitization, a new method for low cost ATG, is discussed. A concurrent fault simulator is used to verify the generated test patterns. Experimental results show that ATWIG is very efficient in generating test patterns for combinational and low sequential circuits. Further improvements and heuristics are necessary for automatic test generation of highly sequential circuits. The relationship between C/O cost measures and A TWIG cost is discussed.

Hardware and software tools for microprocessor functional test

Abstract: The GAPT project (automatic generation of test programs for microprocessors) is in its final phase. The various components of the project (method, software tools and hardware environment) are presented. A strategy to locate failures at a functional level is presented and illustred on an actual faulty circuit.

Parameterized Random Testing

Abstract: Random testing uses random inputs to test digital circuits. A major problem in random testing is the cost to compute the test length which is required for achieving an acceptable fault coverage. Different input distributions on the random inputs produce different fault detection probabilities. Therefore parameterized input distributions are analyzed and analytical methods are given for computing the fault coverage as a function of the parameters. The parameters are chosen so that the fault detection probability is maximized and the test pattern length is minimized. This analytical method of analyzing random test patterns tends to be faster than fault simulation.

Test structures for propagation delay measurements on high-speed integrated circuits

Abstract: The accuracy of high-speed wafer-level measurements on digital IC's is limited by the probe interface. This limitation strongly encourages the use of built-in on-chip test hardware to reduce the number of critical off-chip high-speed interfaces. A novel synchronous propagation delay test structure is described which will provide accurate parametric data under typical automatic test conditions. Built-in test features added to complex combinational circuits are shown which are useful for delay measurement and which reduce the total number of high-speed I/O connections while still providing acceptable fault coverage in many cases.

Codec testing using synchronized analog and digital signals

Abstract: This paper describes the test requirements for operational verification of a CODEC circuit used for telecommunications printed circuit boards and illustrates how the test engineer may utilize five different in-circuit test methods to optimize maximum fault coverage with minimum test time.

Scan path in CMOS semicustom LSI chips

Abstract: The paper presents a scan path design concept evolved to improve the testability of CMOS semicustom LSI chips. Minimizing routing and chip area, avoiding burdens on the layout program, and facilitating automatic test pattern generation are the main goals, achieved by taking into account CMOS semicustom design-specific conditions.

Functional test pattern generation for integrated circuits

Abstract: This paper introduces a new method of generating test patterns for sequential VLSI Circuits. In contrast to traditional methods, all required information is derived from a high level functional specification written in a procedural computer hardware description language. A prototype ATPG system has been implemented and tested on a small model. The results have been very encouraging.

Automatic test pattern generation for asynchronous networks

Abstract: A general description of asynchronous sequential circuits and their testability problems is given. A set of hardware modifications and software modelling techniques is described which allow asynchronous circuits to be tested by scan design techniques.

An Integrated Design for Testability and Automatic Test Pattern Generation System: An Overview

Abstract: A general overview on an Integrated Design for Testability and Automatic Test Pattern Generation System (IDAS) is given. The major components of IDAS include: heuristic controllability/observability (C/O) analysis, prediction of testing costs, tools for evaluation, display and improvement of testability, and C/O guided automatic test pattern generator. The IDAS system includes also the logic and concurrent fault simulator CADAT. A brief description of major components with a scenario how to use IDAS is given. Future research activities are discussed.

A CMOS LSSD test generation system

Abstract: Automatic test pattern generators based on the stuck-fault concept are theoretically inadequate in their ability to generate test patterns for CMOS circuits. A new set of pin faults, called CMOS faults, is discussed that can represent the necessary test pattern sequences for these circuits. Processing of these faults by a new test pattern generator, called the Enhanced Test Generator (ETG), is also described.

Test Generation for LSI: A Case Study

Abstract: A new automatic test generation approach for LSI circuits has been presented in the companion papers [1] [2]. In this paper we generate tests for a typical LSI circuit using the new approach. The goal of this study is to gain insight into the problems involved in using the test generation procedures. A formal model C for a 1-bit microprocessor slice is defined which has all the main features of commercially available bit slices such as the Am2901. The circuit C is modeled as a network of interconnected functional modules. The functions of the individual modules are described using binary decision diagrams, or equivalently using experiments derived from the diagrams. Using our test generation technique, we derive tests for the circuit C capable of detecting various faults covered by our fault model [1]. It is shown that backtracking is rarely needed while generating tests for C. Also, we show that generating a multiple vector test is not required for any of the faults considered in the study. The length of the circuit's test sequence is significantly reduced using the fault collapsing method. A discussion of how to model some of the features of LSI circuits that are not included in the circuit C is presented. A comparison between the length of the test generated by our method and other manually-generated ones is also presented.

Method and structure for testing high voltage circuits

Abstract: A unique method and structure is provided for testing high voltage equipment with great accuracy of voltage levels to be measured, repeatability of measured levels from one piece of test equipment to the next, no need for recalibration of test equipment, and sufficiently low current during testing that the test equipment can be powered by the same supply that powers the device under test. The device of this invention can be used to measure not only logical one and logical zero voltage levels of the device under test while under specific loads but can also be used to meausre transition time from one logic state to another. The circuit of this invention provides an output signal which can have three states reflecting a high logic level from the device under test, a low logic level from the device under test, and an intermediate level indicating that the device under test is in transition from one logic level to another or has failed the test.

A VLSI communication processor designed for testability

Abstract: A 16b processor for control of digital communication networks, with 2186 bytes of RAM will be discussed. The chip features include instruction fault detection, I/O parity check/ generation and special test modes.

VLSI (Very Large Scale Integrated) self-testing using exhaustive bit patterns

Abstract: : The use of Linear Feedback Shift Register functions in generating exhaustive test case coverage for Very Large Scale Integrated circuits with SCAN/SET capability is presented. Both deterministic and probabilistic approaches to test pattern generation are discussed. A technique for signature generation is presented with analysis of its effectiveness. Also, a technique is described for consolidating the test patttern generation and signature capture functions into a single test/detect capability that requires less built-in hardware for implementation.