Showing papers on "Automatic test pattern generation published in 1988"
••
TL;DR: SOCRATES as discussed by the authors is an automatic test pattern generation system for combinational and scan-based circuits based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures.
Abstract: An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment. >
517 citations
••
TL;DR: The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits.
Abstract: An approach to test-pattern generation for synchronous sequential circuits is presented. The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits. Tests for finite-state machines with a large number of states have been successfully generated using reasonable amounts of CPU time and close-to-maximum possible fault coverages have been obtained. For very large sequential circuits, an incomplete scan-design approach to test generation has been developed. The deterministic test generation algorithm is again used to generate test for faults in the modified circuit. All irredundant faults can be detected as in the complete scan design case, but at significantly less area and performance cost. The length of the test sequences for the faults can be bounded by a prescribed value-in general, a tradeoff exists between the number of memory elements required to be made scannable and the maximum allowed length of the test sequence. >
213 citations
••
12 Sep 1988TL;DR: Two linear test algorithms (length 9N and 13N respectively, where N is the number of addresses) plus a data retention test are proposed that cover 100% of the faults under the fault model.
Abstract: A fault model for SRAMs (static random-access memories) is presented based on physical spot defects, which are modeled as local disturbances in the layout of an SRAM. Two linear test algorithms (length 9N and 13N respectively, where N is the number of addresses) plus a data retention test are proposed that cover 100% of the faults under the fault model. The 13N test algorithm is generally applicable while the 9N algorithm can only be used in SRAMs with combinational R/W logic. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms is verified by a large number of actual wafer tests and device failure analysis. >
193 citations
••
12 Sep 1988TL;DR: An algorithm was devised and implemented to automate the process of test generation, and results of experimentation with the ATPG, as well as with a random-pattern simulator, on four ISCAS-85 circuits were reported.
Abstract: The class of faults known as gate delay faults are investigated. A taxonomy of the classes of gate delay fault detecting tests is provided. Methods to derive robust and nonrobust tests to detect gate delay faults are proposed. A physically meaningful measure to assess the efficacy of test sequences is introduced, and used to report fault coverages. A nine-valued logic system was proposed and used for deriving these tests. A physically meaningful measure, in the form of the average detection size of a test sequence. An algorithm was devised and implemented to automate the process of test generation, and results of experimentation with the ATPG, as well as with a random-pattern simulator, on four ISCAS-85 circuits were reported. >
173 citations
••
TL;DR: The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits using a 16-valued logic system, GEMINI, and an extended fault model which includes stuck-at, stuck-open, and delay faults is used.
Abstract: The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits. Input vectors are analyzed in pairs in two steps using a 16-valued logic system, GEMINI. Forward propagation is performed to determine, for each line in the network, the set of all possible values it can take if the network contains any single or multiple faults. Based on the values observed at primary outputs, backward implication is performed to determine the value actually carried by each line. Some deduced values imply the line is not faulty; similarly, some values imply that there is a fault in the subnetwork driving the line, or on the line itself. By keeping track of this information, it is possible to locate a fault to within its equivalence class. An extended fault model which includes stuck-at, stuck-open, and delay faults is used. Multiple faults of all multiplicities are implicitly considered; thus, the results obtained using this method are not invalidated in the presence of untested or untestable lines. >
164 citations
••
27 Jun 1988TL;DR: Based on the sophisticated strategies used in the automatic test pattern generation system SOCRATES, this article presented several concepts aiming at a further improvement and acceleration of the deterministic test pattern generator and redundancy identification process.
Abstract: Based on the sophisticated strategies used in the automatic test pattern generation system SOCRATES, the authors present several concepts aiming at a further improvement and acceleration of the deterministic test pattern generation and redundancy identification process. In particular, they describe an improved implication procedure and an improved unique sensitization procedure. Both procedures significantly advance the deterministic test pattern generation and redundancy identification especially for those faults, for which it is difficult to generate a test pattern or to prove them to be redundant, respectively. As a result of the application of the proposed techniques, SOCRATES is capable of successfully generating a test pattern for all testable faults in a set of combinational benchmark circuits, and of identifying all redundant faults with less than 10 backtrackings. >
158 citations
01 Jan 1988
TL;DR: An improved implication procedure and an improved unique sensitization procedure significantly advance the deterministic test pattern generation and redundancy identification especially for those faults, for which it is difficult to generate a test pattern or to prove them to be redundant, respectively.
Abstract: Based upon the sophisticated strategies used in the automatic test pattern generation system SOCRATES, this paper presents several new concepts aiming at a further improvement and acceleration of the deterministic test pattern generation and redundancy identification process. In particular, we will describe an improved implication procedure and an improved unique sensitization procedure. Both procedures significantly advance the deterministic test pattern generation and redundancy identification especially for those faults, for which it is difficult to generate a test pattern or to prove them to be redundant, respectively. As a result of the application of the proposed techniques, SOCRATES is capable of successfully generating a test pattern for all testable faults in a set of combinational benchmark circuits, and of identifying all redundant faults with less than 10 backtrackings.
157 citations
••
TL;DR: In this scan design methodology, only selected faults are targeted for detection, and the use of flip-flops is avoided as much as possible during test generation.
Abstract: In this scan design methodology, only selected faults are targeted for detection. These faults are those not detected by the designer's functional vectors. The test generator decides exactly which flip-flops should be scanned using one of two methods. In the first method, all possible tests are generated for each target fault, and the set of tests requiring the fewest flip-flops is selected. In the second method, only one test is generated for each fault, and the use of flip-flops is avoided as much as possible during test generation. Examples of actual VLSI circuits show a savings of at least a 40% in full-scan overhead. >
120 citations
••
IBM1
TL;DR: An approach to test for delay faults is presented, using a variable size delay fault model to represent these failures and determining the quality of detection measures how close the test came to exposing the ideally smallest-size fault at that point.
Abstract: An approach to test for delay faults is presented. A variable size delay fault model is used to represent these failures. The nominal gate delays with the manufacturing tolerances are an integral part of the model and are used in the propagation of simplified waveforms through the logic network. The faulty waveforms are functions of the variable-size delay fault. For each fault and test pattern, a threshold is computed such that this fault is detected if its size exceeds epsilon . This threshold is used (along with the minimum slack at the fault site) to determine a metric called quality. The quality of detection for a fault measures how close the test came to exposing the ideally smallest-size fault at that point. This metric (together with the traditional fault coverage) gives a complete measure of the goodness of the test. >
101 citations
••
12 Sep 1988TL;DR: A novel test-generation technique for large circuits with high fault-coverage requirements is described, which shows that a substantial increase in test generation speed can be achieved.
Abstract: A novel test-generation technique for large circuits with high fault-coverage requirements is described. Circuit modules and signals are represented at a high descriptive level. Test data for modules are represented by predefined stimulus/response packages which are processed symbolically using techniques derived from artificial intelligence. Since many test vectors are processed simultaneously, a substantial increase in test generation speed can be achieved. Preliminary results from a programmed implementation of the proposed test-generation technique are presented. >
99 citations
••
01 Jun 1988TL;DR: The application of a concurrent fault simulator to automatic test vector generation is described, and results are presented showing the effectiveness of this method in generating tests for combinational and sequential circuits.
Abstract: The application of a concurrent fault simulator to automatic test vector generation is described. As faults are simulated in the fault simulator, a cost function is simultaneously computed. A simple cost function is the distance (in terms of the number of gates and flip-flops) of a fault effect from a primary output. The input vector is then modified to reduce the cost function until a test is found. The authors present experimental results showing the effectiveness of this method in generating tests for combinational and sequential circuits. By defining suitable cost functions, they have been able to generate: (1) initialization sequences, (2) tests for a group of faults, and (3) a test for a given fault. Even asynchronous sequential circuits can be handled by this approach. >
••
TL;DR: With this method, the length of time required for all of the test vectors to appear, possibly in some order, among the normal inputs to the circuit under test is of considerable importance.
Abstract: A method is presented for testing digital circuits during normal operation. The resources used to perform online testing are those which are inserted to alleviate the offline testing problem. The offline testing resources are modified so that during system operation they can also observe the normal inputs and outputs of a combinational circuit under test. The normal inputs to the circuit under test are with test vectors in its test set. When a normal input matches a test vector, the circuit output for such an input is typically compressed into a developing signature. When all of the test vectors in the test set have appeared as normal inputs, the signature is read and verified. With this method, the length of time required for all of the test vectors to appear, possibly in some order, among the normal inputs to the circuit under test is of considerable importance. >
••
01 Jun 1988
TL;DR: Preliminary results are presented which indicate that the method provides a higher robust delay fault coverage than pseudorandom patterns at less than one-fifth the cost.
Abstract: It has been observed that random testing for delay faults can result in test sets of excessive length and high simulation costs. Consequently, we propose an efficient deterministic method of delay fault test generation. For most common circuits, our proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. We define a type of transition path, the fully transitional path, FTP, and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input, a technique introduced in [1]. We extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that our method provides a higher robust delay fault coverage than psuedorandom patterns at less than one-fifth the cost. Also, since vector pairs cannot be applied to combinational circuits using standard scan design, a simple scannable latch is introduced to facilitate this task.
••
12 Sep 1988TL;DR: An incomplete scan design approach to sequential test generation is presented, which represents a significant departure from previous methods and can be guaranteed as in the complete scan design case, but at significantly less area and performance cost.
Abstract: An incomplete scan design approach to sequential test generation is presented. This approach represents a significant departure from previous methods. First, using an efficient sequential testing algorithm, test sequences are generated for a large number of possible faults in the given sequential circuit. A minimal subset of memory elements is then found, which if made observable and controllable will result in easy detection of the sequentially redundant and irredundant but difficult-to-defect faults. The deterministic test generation algorithm is again used to generate tests for these faults in the modified circuit (the circuit with the identified memory elements made scannable). Detection of all irredundant faults can be guaranteed as in the complete scan design case, but at significantly less area and performance cost. >
••
IBM1
TL;DR: A novel algebra is introduced for delay test generation that combines the nine natural logic values with special attributes that record both heuristic choices and whatever information about waveforms is deducible algebraically (i.e. without numerical computations using actual gate delays).
Abstract: For pt.I see ibid., p.857-66 (1988). A novel algebra is introduced for delay test generation. The algebra combines the nine natural logic values (00 , 01, 0X, 10, 11, 1X, X1, XX) with special attributes that record both heuristic choices and whatever information about waveforms is deducible algebraically (i.e. without numerical computations using actual gate delays). A test generator uses this algebra in an efficiently organized backtrack search. The test generator is linked to a delay fault simulator. Previous event-driven simulators have considered different types of events; one type of event is a change in faultless values from one test to another test, and the other type of event is a difference between faulty and faultless values. The presented simulator is driven by both types of events. Each generated test is simulated to determine the quality of detection. >
••
TL;DR: Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency, using a modified linear-feedback shift register to generate exhaustive test patterns for every output of the circuit.
Abstract: Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to generate exhaustive test patterns for every output of the circuit. All detectable, combinational faults (those that do not change a combinational circuit to a sequential circuit) in each cone of logic driving a single output are guaranteed to be detected. Examples indicate that LFSRs based on cyclic codes have lower hardware cost and shorter or comparable test lengths than other approaches. These test-pattern generators are well suited to applications where short testing time, low hardware overhead, and 100% single-stuck-at fault coverage are required. >
••
12 Sep 1988TL;DR: It is shown that, not only is fault grading required, but that extremely high single stuck fault coverage is probable necessary, and the need for extremely thorough testing is demonstrated.
Abstract: The authors examine the question of whether fault grading is necessary and if yes, how high the single-stuck fault coverage must be? They show that, not only is fault grading required, but that extremely high single stuck fault coverage is probable necessary. The results presented are extensions of previous work in this area by T.W. Williams (1985). The authors discuss only functional or Boolean testing, which does not involve measurement, but determines whether logic functions are correct. The question of how thorough a Boolean test procedure need be is the main focus. The need for extremely thorough testing is demonstrated. >
••
01 Jun 1988TL;DR: A novel circuit model, SPLIT, is presented which is a modified 9-valued circuit model which has the precision of the 9- valued model and the simplicity of the 5-valued model.
Abstract: Over the years, the D-algorithm has been successfully used to generate tests for sequential circuits and combinational circuits. There are 5-valued and 9-valued circuit models used for the D-algorithm. The disadvantage of a model with lower value count is its inability to assign a more precise value for a test generation requirement without some undue assumptions or decisions which may cause backtracks or even may find no test for testable faults. However, the availability of more values increases the search space and makes enumeration more complicated. In this paper, we will present a new circuit model SPLIT which is a modified 9-valued circuit model. SPLIT has the precision of the 9-valued model and the simplicity of the 5-valued model, such that the D-algorithm will have better performance using the SPLIT model than using the 5-valued model or the 9-valued model.
••
01 Dec 1988TL;DR: Based on novel heuristic techniques, a program has been written in C that achieved a 56%-73% reduction in the test length of a highly sequential circuit obtained from industry.
Abstract: Currently available automatic test pattern generators (ATPGs) generate test sets that are nonoptimal in length. The authors describe novel heuristic techniques to reduce the length of the test set for a sequential circuit by compaction of the automatically generated patterns. Based on these techniques, a program has been written in C that achieved a 56%-73% reduction in the test length of a highly sequential circuit obtained from industry. >
••
TL;DR: Experimental results are given which indicate that, with the exception of the don't-care method, each of these methods has a problem class in which it is clearly superior to the others.
Abstract: A description is given of a theory for, and the application of, a general algorithm for determining whether a given multilevel Boolean function is a tautology or whether two given multilevel Boolean functions are equivalent. Four specific cases of this general algorithm are examined. These are termed the flattening method, the don't-care method, the simulation method, and the algebraic string comparison method. A single unifying algorithm frame is given for the implementation of any of these four methods, depending on parameterization. Experimental results are given which indicate that, with the exception of the don't-care method, each of these methods has a problem class in which it is clearly superior to the others. The primary application of these algorithms is as a verification tool for silicon compilation systems. However, these algorithms are also being used as the foundation for multilevel logic minimization and automatic test pattern generation programs. >
••
12 Sep 1988TL;DR: A self-test machine for static random access memories (SRAMs) has been developed that is capable of running linear test algorithms, generating a at a retention test and generating a number of data backgrounds.
Abstract: A self-test machine for static random access memories (SRAMs) has been developed. It is capable of running linear test algorithms, generating a at a retention test and generating a number of data backgrounds. The test algorithm implemented has excellent fault-detection capabilities and is extremely regular and symmetric, which results in a minimum of hardware overhead and performance loss. Self-test reduces the possibilities for diagnostic tests. A form of scan test remains necessary in spite of a self-test implementation. This self-test design offers full scan test facilities of both the SRAM and the self-test logic itself. This version of the SRAM self-test is currently being implemented in a number of digital signal processing chips and will, after a final evaluation, be used for a broad scope of designs. >
••
TL;DR: A heuristic is described for evaluating the multiple fault coverage of single stuck-at fault test sets and a second heuristic generates augmented test sets, providing improved multiple stuck- at fault coverage with a minimal increase in test set development cost.
Abstract: A simulation study of the 74LS181 4-b ALU (arithmetic logic unit) using 16 complete single stuck-at fault test sets demonstrated significantly higher multiple stuck-at fault coverage than predicted by previous theoretical studies. Analysis of the undetected multiple faults shows the effect of circuit and test set characteristics on fault coverage. A fault masking property, defined as self-masking, is observed for the undetected faults in the simulation study. A heuristic is described for evaluating the multiple fault coverage of single stuck-at fault test sets. A second heuristic generates augmented test sets, providing improved multiple stuck-at fault coverage with a minimal increase in test set development cost. >
•
29 Jul 1988TL;DR: In this article, the authors present a method and apparatus to estimate fault coverage of a set of test vectors to be applied to a circuit containing sequential elements by taking into account the external state of the sequential element during circuit simulation.
Abstract: Method and apparatus estimates fault coverage of a set of test vectors to be applied to a circuit containing sequential elements. The apparatus permits sequential elements to be represented as functional blocks rather than combinational circuits with feedback. This is accomplished by taking into account the external state of the sequential element during circuit simulation. The apparatus also takes into account high impedance as possible inputs and outputs.
••
27 Mar 1988TL;DR: In this paper, the authors present an estimation of fault coverage of four protocol test sequences generation techniques (T-, U-, D-, and W-methods) using Monte Carlo simulation on a simple protocol machine.
Abstract: The authors present an estimation of fault coverage of four protocol test sequences generation techniques (T-, U-, D-, and W-methods) using Monte Carlo simulation on a simple protocol machine. The ability of a test sequence to decide whether a protocol implementation conforms to its specification heavily relies upon the range of faults that it can capture. This study shows that a test sequence produced by T-method has a poor fault detection capability whereas test sequences produced by U-, D- and W-methods have fault coverage comparable to each other and superior to that for T-method on several classes of randomly generated machines used. >
••
27 Jun 1988TL;DR: The authors have delimited, for every convergent fanout stem, a region of the circuit outside of which the stem fault does not have to be simulated, and the fault simulation complexity of a circuit is shown to be directly related to the number and size of stem regions in the circuit.
Abstract: An exact fault simulation can be achieved by simulating only the faults on reconvergent fanout stems, while determining the detectability of faults on other lines by critical path tracing within fanout-free regions. The authors have delimited, for every convergent fanout stem, a region of the circuit outside of which the stem fault does not have to be simulated. Lines on the boundary of such a stem region, called exit lines, have the following property: if the stem fault is detected at the line, and the line is critical with respect to a primary output, then the stem fault is detected at the primary output. Any fault-simulation technique can be used to simulate the stem fault within its stem region. The fault simulation complexity of a circuit is shown to be directly related to the number and size of stem regions in the circuit. Results obtained for the well-known benchmark circuits are presented. >
••
01 Jun 1988TL;DR: A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described, resulting in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments.
Abstract: Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments. >
••
TL;DR: It is shown that a test set based on two-pattern tests, which are designed to detect single stuck-open faults, can be found that detects all multiple stuck- open faults inside any CMOS gate in the circuit.
Abstract: It is shown that a test set based on two-pattern tests, which are designed to detect single stuck-open faults, can be found that detects all multiple stuck-open faults inside any CMOS gate in the circuit. The concept is extended to three-pattern tests, which are obtained for every single stuck-open fault at the checkpoints. If a certain condition is satisfied, then it can be shown that the resulting test set can detect any multiple stuck-open fault in the circuit. Even when this condition is not fully met, a very large percentage of the multiple stuck-open faults can still be guaranteed to be detected. For the special case of fan-out-free CMOS circuits, it is shown that a single stuck-open fault test set based on two-pattern tests can always be found that has 100% multiple stuck-open fault coverage. This test can also be guaranteed to be robust in the presence of arbitrary delays. >
••
TL;DR: The author introduces the concept of test generation and analyzes the way each algorithm uses search and backtracking techniques to sensitize a fault and propagate it to an observable point.
Abstract: Three well-known algorithms for the automatic test pattern generation (ATPG) for digital circuits are the D algorithm, Podem, and Fan. The author introduces the concept of test generation and analyzes the way each algorithm uses search and backtracking techniques to sensitize a fault and propagate it to an observable point. The heuristics used to guide ATPG search and the notation used to represent circuit values are examined. >
••
01 Jan 1988TL;DR: An automatic test pattern generation (ATPG) methodology that has the potential to exploit fine-grain parallel computing and relaxation techniques is described and preliminary results on combinational circuits confirm the feasibility of the technique.
Abstract: An automatic test pattern generation (ATPG) methodology that has the potential to exploit fine-grain parallel computing and relaxation techniques is described. The approach is radically different from the conventional methods used to generate tests for circuits from their gate-level descriptions. A digital circuit is represented as a bidirectional network of neurons. The circuit function is coded in the firing thresholds of neurons and the weights of interconnection links. This neural network is suitably reconfigured for solving the ATPG problem. A fault is injected into the neural network and an energy function is constructed with global minima at test vectors. Global minima are determined by a probabilistic relaxation technique augmented by a directed search. Preliminary results on combinational circuits confirm the feasibility of the technique. >
••
TL;DR: The design of two well-known optimal time adders are considered: the carry look-ahead adder and the conditional sum adder, which are considered pertinent to establishing the correct behavior of a given VLSI chip.
Abstract: Considers the design of two well-known optimal time adders: the carry look-ahead adder and the conditional sum adder. It is shown that 6 log/sub 2/(n)-4 and 6 log/sub 2/(n)+2 test patterns suffice to completely test the n-bit carry look-ahead adder and the n-bit conditional sum adder with respect to the single stuck-at fault model (for a given set of basic cells). The results are considered pertinent to establishing the correct behavior of a given VLSI chip. >