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Showing papers on "Automatic test pattern generation published in 1989"


Proceedings ArticleDOI
08 May 1989
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Abstract: A set of 31 digital sequential circuits described at the gate level is presented. These circuits extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-based test generation, and mixed sequential/scan-based test generation using partial scan techniques. Although all the benchmark circuits are sequential, synchronous, and use only D-type flip-flops, additional interior faults and asynchronous behavior can be introduced by substituting for some or all of the flip-flops their appropriate functional models. The standard functional model of the D flip-flop provides a reference point that is independent of the faults particular to the flip-flop implementation. A testability profile of the benchmarks in the full-scan-mode configuration is discussed. >

1,972 citations


Journal ArticleDOI
TL;DR: A description of Gentest, with emphasis on STG2, a sequential test generator that uses the Back test-generation algorithm and the Split value model, and results for another set of experiments for Gentest on a Sun 3/60 workstation.
Abstract: A description is given of Gentest, with emphasis on STG2, a sequential test generator that uses the Back test-generation algorithm and the Split value model. The performance of STG2 on a Convex C-1 computer is compared with that of its predecessor, STG1 and STG1.5. Results are also presented for another set of experiments for Gentest on a Sun 3/60 workstation. >

202 citations


Proceedings ArticleDOI
N. Jarwala1, C.W. Yau1
29 Aug 1989
TL;DR: A novel framework for analyzing test generation and diagnosis algorithms for wiring interconnect are presented, and a property of test vector sets, called diagonal independence, which guarantees the diagnostic resolution of the vector test set is identified.
Abstract: A novel framework for analyzing test generation and diagnosis algorithms for wiring interconnect are presented. A property of test vector sets, called diagonal independence, which guarantees the diagnostic resolution of the vector test set is identified. The failing responses or syndromes are classified into aliasing and confounding syndromes, and this classification permits precise analysis of the diagnostic capabilities of different test algorithms. Using this framework, all the algorithms that have been proposed for board interconnect testing are analyzed. Their capabilities and limitations are clearly defined. A new optimal adaptive algorithm that can reduce test and diagnosis complexity is also presented. >

166 citations


Proceedings ArticleDOI
21 Jun 1989
TL;DR: A method of partial scan design in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit is presented, and experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit.
Abstract: A method of partial scan design in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit is presented. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles to reduce sequential depth. Tests for the resulting circuit can be efficiently generated by a sequential logic test generator. An independent control of the scan clock allows the insertion of scan sequences within the vector sequence produced by the test generator. Experimental results on a 5000 gate circuit show that a test coverage above 98% could be obtained by scanning just 5% of the flip-flops. In addition, the authors give the design of a scan flip-flop to reduce the input pin and signal routing overheads in a single-clock design. >

103 citations


Journal ArticleDOI
TL;DR: Experimental results are presented showing the effectiveness of the application of a concurrent fault simulator to automatic test vector generation in generating tests for combinational and sequential circuits.
Abstract: A description is given of the application of a concurrent fault simulator to automatic test vector generation. As faults are simulated in the fault simulator a cost function is simultaneously computed. A simple cost function is the distance (in terms of the number of gates and flip-flops) of a fault effect from a primary output. The input vector is then modified to reduce the cost function until a test is found. Experimental results are presented showing the effectiveness of this method in generating tests for combinational and sequential circuits. By defining suitable cost functions, it has been possible to generate: (1) initialization sequences; (2) tests for a group of faults; and (3) a test for a given fault. Even asynchronous sequential circuits can be handled by this approach. >

97 citations


Proceedings ArticleDOI
21 Jun 1989
TL;DR: The authors propose a ten-valued logic and describe the corresponding implication and path sensitization procedures in detail and discuss an extended multiple backtrace procedure, which has been developed specifically to meet the requirements of path delay testing.
Abstract: Based on the sophisticated techniques applied in the automatic test pattern generation system SOCRATES, the authors present the extension of SOCRATES to test generation for path delay faults. In particular, they propose a ten-valued logic and describe the corresponding implication and path sensitization procedures in detail. After discussing an extended multiple backtrace procedure, which has been developed specifically to meet the requirements of path delay testing, they conclude with a number of experimental results. >

92 citations


Proceedings ArticleDOI
T. Larrabee1
29 Aug 1989
TL;DR: A novel system is described that is able to test or improve untestable every fault in the popular Brglez-Fujiwara test benchmark and can incorporate any of the heuristics used by structural search techniques.
Abstract: Most automatic test pattern generation systems for combinational circuits generate a test for a given fault by directly searching a data structure representing the circuit to be tested. The author describes a novel system that divides the problem into two parts: first it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits. Second, it applies a Boolean satisfiability algorithm to the resulting formula. The novel system can incorporate any of the heuristics used by structural search techniques. It is not only quite general but is able to test or improve untestable every fault in the popular Brglez-Fujiwara test benchmark (Int. Symp. Circuits and Systems, June 1985). Experimental results are presented. >

90 citations


Proceedings ArticleDOI
21 Jun 1989
TL;DR: In the proposed partial scan methodology, the scan path is constructed so that the rest of the circuit belongs to a class of circuits called balanced sequential structures, and test patterns for this structure are generated by treating it as being combinational.
Abstract: In the proposed partial scan methodology, the scan path is constructed so that the rest of the circuit belongs to a class of circuits called balanced sequential structures. Test patterns for this structure are generated by treating it as being combinational. Each test pattern is applied to the circuit by shifting it into the scan path. holding it constant for a fixed number of clock cycles, loading the test result into the scan path, and then shifting it out. This technique achieves full coverage of all detectable faults with a minimal number of scannable storage elements and using only combinational test pattern generation. >

88 citations


Proceedings ArticleDOI
05 Nov 1989
TL;DR: An efficient sequential circuit test generation algorithm is presented that is based on PODEM and uses a nine-valued logic model and uses an initial time-frame algorithm to solve the previous state information problem.
Abstract: An efficient sequential circuit test generation algorithm is presented. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of an initial time-frame algorithm and correct implementation of a solution to the previous state information problem. The initial time-frame algorithm determines the number of time-frames required to excite the fault under test and the number of time-frames required to observe the excited fault. This step saves the test generator from doing unnecessary search in the input space. Test generation is done strictly in forward time. The algorithm saves good machine circuit state after test generation to aid in future test generation. Faulty machine state is set to unknown whenever test generation for a fault is begun. This solves the previous state information problem, which has often been ignored by existing test generators. >

87 citations


Proceedings ArticleDOI
01 Aug 1989
TL;DR: The authors present a novel test procedure that exploits both the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit, and describe fast algorithms for state justification and state differentiation using the ON sets and OFF sets of flip-flop inputs and primary outputs.
Abstract: The authors address the problem of generating test sequences for stuck-at faults in nonscan synchronous sequential circuits. They present a novel test procedure that exploits both the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit. In contrast to previous approaches, the authors decompose the problem of sequential test generation into three subproblems of combinational test generation, fault-free state justification, and fault-free state differentiation. They describe fast algorithms for state justification and state differentiation using the ON sets and OFF sets of flip-flop inputs and primary outputs. The decomposition of the testing problem into three subproblems rather than the traditional two, performing the justification and differentiation steps on the fault-free rather than the faulty machine, and the use of efficient techniques for cube intersection result in significant performance improvements over previous approaches. >

85 citations


Proceedings ArticleDOI
05 Nov 1989
TL;DR: A diagnosis method is proposed which may be used to locate faults in circuits tested with random or pseudorandom test vectors, and which uses offline posttest simulation to isolate a single fault with only a fraction of the simulation that would ordinarily be required.
Abstract: A diagnosis method is proposed which may be used to locate faults in circuits tested with random or pseudorandom test vectors. No intermediate signatures are involved, and the external hardware required is not complex. This proposed diagnosis scheme, called DAPPER, is applicable to multioutput combinational circuits. DAPPER classifies faults initially by their detection probability for coarse resolution, and secondly using their first failing pattern and a conventional signature for fine resolution. This method uses offline posttest simulation to isolate a single fault with only a fraction of the simulation that would ordinarily be required. Additionally, any failures within the test hardware itself may be diagnosed using the method. >

Proceedings ArticleDOI
29 Aug 1989
TL;DR: The authors present ESSENTIAL, deterministic automatic test pattern generation algorithm for sequential circuits that avoids the detrimental a priori determination of a topological path to be sensitized or of a primary output, to which the fault effects have to be propagated.
Abstract: The authors present ESSENTIAL, deterministic automatic test pattern generation algorithm for sequential circuits. By combining reverse time processing over time frames and forward processing within time frames, ESSENTIAL avoids the detrimental a priori determination of a topological path to be sensitized or of a primary output, to which the fault effects have to be propagated. Moreover, the proposed test generation approach fully exploits the beneficial techniques that have successfully been used for combinational circuits by the automatic test pattern generation system SOCRATES. In particular, the authors discuss a learning procedure for global implications not only over reconvergent fanout, but also over time frames as well as static and dynamic unique sensitization techniques. After introducing a couple of intelligent heuristics employed for guiding and supporting the decision-making process, the authors report some preliminary but encouraging experimental results. >

Proceedings ArticleDOI
29 Aug 1989
TL;DR: A test sequence is given for the test access port (TAP) controller portion of the boundary-scan architecture proposed by the Joint Test Action Group (JTAG) and IEEE Working Group P1149.1 as an industry-standard design-for-testability technique.
Abstract: A test sequence is given for the test access port (TAP) controller portion of the boundary-scan architecture proposed by the Joint Test Action Group (JTAG) and IEEE Working Group P1149.1 as an industry-standard design-for-testability technique. The resulting test sequence, generated by using a technique based on Rural Chinese Postman tours and unique input/output sequences, is of minimum cost (time) and rigorously tests the specified functional behavior of the controller. The test sequence can be used for detecting design faults for conformance testing or for detecting manufacture-time/run-time defects/faults. >

Journal ArticleDOI
TL;DR: An upper bound is found for the minimum number of test patterns required to detect a fault in combinational networks based on Reed-Muller (RM) transforms.
Abstract: A new approach for fault detection in combinational networks based on Reed-Muller (RM) transforms is presented. An upper bound on the number of RM spectral coefficients required to be verified for detection of multiple stuck-at-faults and single bridging faults at the input lines of an n-input network is shown to be n. The time complexity (time required to test a network) for detection of multiple terminal faults and the storage required for storing the test are determined. An upper bound is found for the minimum number of test patterns required to detect a fault. The authors present standard tests based on this result, with a simple test generation procedure and upper bounds on minimal numbers of test patterns. >

Proceedings ArticleDOI
05 Nov 1989
TL;DR: The authors demonstrate that test vectors can be generated using realistic defect models and actual IC layouts, which should lead to test vectors with a higher defect detectability.
Abstract: Conventionally, test vectors are generated using gate-level models to represent the circuit design and abstract fault models (e.g. the stuck-fault model) to describe all of the processing defects causing circuit failure. The authors demonstrate that test vectors can be generated using realistic defect models and actual IC layouts, which should lead to test vectors with a higher defect detectability. The layout-driven generation of the faults has a computational complexity which is similar to that of design-rule checking, i.e. O(n log n). >

Proceedings ArticleDOI
29 Aug 1989
TL;DR: The authors propose a load-balancing method which uses static partitioning initially and then dynamic allocation of work for processors which become idle and present experimental results based on an implementation on the Intel iPSC/2 hypercube multiprocessor using the ISCAS combinational benchmark circuits.
Abstract: The authors address the issues involved in providing an integrated test generation/fault simulation environment on a parallel processor. They propose heuristics to partition faults for parallel test generation with minimization of the overall run time and test length as an objective. For efficient utilization of available processors, the work load has to be balanced at all times. Since it is very difficult to predict a priori how difficult it is to generate a test for a particular fault, the authors propose a load-balancing method which uses static partitioning initially and then dynamic allocation of work for processors which become idle. They present experimental results based on an implementation on the Intel iPSC/2 hypercube multiprocessor using the ISCAS combinational benchmark circuits. The main contribution of the work described is to show that if one is not careful in the design of a parallel algorithm, apart from inefficient utilization of available processors, degradation in the quality of solutions can occur. >

Patent
27 Mar 1989
TL;DR: In this paper, a data input multiplexer between the test nodes of the circuit under test and the signature inspection logic can provide for identification of the specific node at fault by the Signature inspection logic.
Abstract: A system and method for fault detection for electronic circuits. A stimulus generator sends a signal to the input of the circuit under test. Signature inspection logic compares the resultant signal from test nodes on the circuit to an expected signal. If the signals do not match, the signature inspection logic sends a signal to the control logic for indication of fault detection in the circuit. A data input multiplexer between the test nodes of the circuit under test and the signature inspection logic can provide for identification of the specific node at fault by the signature inspection logic. Control logic responsive to the signature inspection logic conveys information about fault detection for use in determining the condition of the circuit. When used in conjunction with a system test controller, the built-in test by signature inspection system and method can be used to poll a plurality of circuits automatically and continuous for faults and record the results of such polling in the system test controller.

Proceedings ArticleDOI
01 Jun 1989
TL;DR: In this article, a testability solution is proposed in which externally accessible test points are pre-designed into cells that comprise the VLSI designs, accessed through an on-chip grid of orthogonal probe and sense lines.
Abstract: A new testability solution is proposed in which externally accessible test points are pre-designed into cells that comprise the VLSI designs. The test points are accessed through an on-chip grid of orthogonal probe and sense lines. The resultant VLSI design consists of a large number of test points through which test signals on every cell on the IC can be measured or modified to a limited extent. The sizable number of test points improves the testability of the designs by a very large factor. Additionally, analog measurement and signal injection capabilities allow detection of practical CMOS fault modes such as opens, shorts, open or closed FETs and even noise margins. The large observability of CrossCheck based designs reduces the automatic test pattern generation problem to one of providing control only. Several ISCAS benchmark designs are analyzed using CrossCheck cell libraries and fault models. The results show that over 97 percent coverage of a broad range of fault modes, such as opens and shorts, can be obtained on VLSI CMOS designs without the need for large computing resources.

Patent
19 Oct 1989
TL;DR: A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality is presented in this paper. But it does not use the same buses to transfer test results out of the integrated circuit under test to be interpreted by the test processor.
Abstract: A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality. The invention uses the power and capability of existing address and data buses to transfer test data into the integrated circuit under boundary scan test, and uses the same buses to transfer test results out of the integrated circuit under test to be interpreted by the test processor of the system.

01 Jan 1989
TL;DR: In this article, the authors present results of an extensive study of five existing testability measures when used to aid heuristics for automatic test pattern generation algorithms, using over 60 000 faults in circuits of varying size and complexity.
Abstract: This paper presents results of an extensive study of five existing testability measures when used to aid heuristics for automatic test pattern generation algorithms. Each measure was evaluated using over 60 000 faults in circuits of varying size and complexity. The per- formance of these measures was rated using several different criteria. Based on these results the performance of a composite test generation strategy that uses multiple guidance heuristics was evaluated. The re- sults indicate that this strategy not only provides better fault coverage but also reduces the average time taken to generate a test or determine that a given fault is undetectable.

Journal ArticleDOI
TL;DR: A way to merge boundary scan with the built-in self-test (BIST) of printed circuit boards with the advantages of the CA register, which allows modification without major redesign, its higher stuck-at fault coverage, and its higher transition fault coverage.
Abstract: The authors propose a way to merge boundary scan with the built-in self-test (BIST) of printed circuit boards. Their boundary-scan structure is based on Version 2.0 of the Joint Task Action Group's recommendations for boundary scan and incorporates BIST using a register based on cellular automata (CA) techniques. They examine test patterns generated from this register and the more conventional linear-feedback shift register. The advantages of the CA register, or CAR, are its modularity, which allows modification without major redesign, its higher stuck-at fault coverage, and its higher transition fault coverage. >

Proceedings ArticleDOI
29 Aug 1989
TL;DR: The authors present the extension of the ATPG system SOCRATES to hierarchical test pattern generation, which is based upon HLPs and the strategy of dynamically expanding the HLPs to their gate-level realization, at most one at a time.
Abstract: It is demonstrated that the exploitation of high-level primitives (HLPs) and, in particular, of the knowledge concerning their function in ATPG (automatic test pattern generation) leads to significant improvements in implication, unique sensitization, and multiple backtrace. Motivated by this observation and the necessity of covering all faults inside HLPs, the authors present the extension of the ATPG system SOCRATES to hierarchical test pattern generation, which is based upon HLPs and the strategy of dynamically expanding the HLPs to their gate-level realization, at most one at a time. Experimental results have substantiated that the proposed approach performs significantly better in terms of CPU time, elapsed time, fault coverage, and memory requirements than a gate-level ATPG algorithm. It is expected that the extended SOCRATES algorithm will be capable of coping with circuits consisting of 100000 gates and more within reasonable times, even in a workstation environment. >

Proceedings ArticleDOI
05 Nov 1989
TL;DR: A method is proposed to determine all the possible ranges of detected fault sizes, thereby maximizing the fault coverage of a given test sequence, and methods are given to achieve such coverages wherever possible.
Abstract: Existing methodologies for determining gate delay fault coverages through the computation of detected fault sizes are shown to have certain deficiencies A method is proposed to determine all the possible ranges of detected fault sizes, thereby maximizing the fault coverage of a given test sequence The ultimate goal of ensuring that the coverage for a particular fault extends up to the actual circuit slack is explored, and methods are given to achieve such coverages wherever possible Results of experiments performed to evaluate the practical benefits of the proposed methods are reported >

Journal ArticleDOI
TL;DR: The design of a versatile module test and maintenance controller (MMC) that can be implemented as a single-chip ASIC (application-specific integrated circuit) or by off-the-shelf components is presented.
Abstract: The design of a versatile module test and maintenance controller (MMC) is presented. Driven by structures test programs, an MMC is able to test every chip in a module or PCB via a test bus. More than one test bus can be controlled by an MMC, and can support several bus architectures and many modes of testing. The differences between MMCs on different modules are the test programs that they execute, the number of test buses they control, and the expansion units they use. A simple yet novel circuit, called a test channel, is used in an MMC. The MMC processor can control a test channel by reading/writing its internal registers. Once initialized by the MMC processor, a test channel can carry out most of the testing of a chip. Thus the processor need not deal with detailed test-bus control sequences since they are generated by the test channel. This strategy greatly simplifies the development of test programs. The proposed MMC can be implemented as a single-chip ASIC (application-specific integrated circuit) or by off-the-shelf components. Some of its self-test features are presented. >

Proceedings ArticleDOI
21 Jun 1989
TL;DR: In this paper, a method is described for selecting a minimal set of directly accessible flip-flops, which is shown to be NP-complete and suboptimal solutions can be derived using some heuristics.
Abstract: A method is described for selecting a minimal set of directly accessible flip-flops. Since this problem turns out to be NP-complete, suboptimal solutions can be derived using some heuristics. An algorithm is presented to compute the corresponding weights of the patterns, which are time-dependent in some cases. The entire approach is validated with the help of examples. Only 10-40% of the flip-flops have to be integrated into a partial scan path or into a built-in self-test register to obtain nearly complete fault coverage by weighted random patterns. >

Proceedings ArticleDOI
Peter Hansen1
29 Aug 1989
TL;DR: The test of embedded clusters of conventional logic via boundary scan virtual channels has been shown to be a practical way to test and diagnose structural faults where these clusters are inaccessible to standard ATE (automatic test equipment) channels.
Abstract: The test of embedded clusters of conventional logic via boundary scan virtual channels has been shown to be a practical way to test and diagnose structural faults where these clusters are inaccessible to standard ATE (automatic test equipment) channels. Huge quantities of data can be created by this technique, which could result in prohibitive storage requirements and poor throughput. By use of topological data compression and special hardware, the storage requirement can be small and test times limited only by the speed of the boundary scan path. After discussing test pattern generation, the boundary scan environment, and the serialization of test patterns and algorithmic patterns, the author presents applications examples. >

Proceedings ArticleDOI
02 Oct 1989
TL;DR: A complete test pattern generation system for path delay faults using PODEM using a 5-valued logic and criteria and efficient algorithms to prune the number of paths for test generation are presented.
Abstract: A complete test pattern generation system for path delay faults is presented. The test pattern generator is based on PODEM using a 5-valued logic. Techniques to prune the search space for test pattern generation are proposed. Since the number of paths for test generation can be exponential in the number of lines in the network, criteria and efficient algorithms to prune the number of paths for test generation are presented. The test generation system is evaluated using the ISCAS combinational benchmark circuits. >

Journal ArticleDOI
K.D. Wagner1, T.W. Williams
TL;DR: The authors provide a set of design for testability (DFT) principles that enhance their ability to test these networks when combined with the requisite analog test plans.
Abstract: The testing of analog/digital integrated circuits is difficult since they allow direct access to relatively few signals. Since the probing of component pins is the fundamental chip production test technique (and possibly that of board test as well, i.e. in-circuit test), methods must be found to enhance the controllability and observability of internal signal networks. The authors provide a set of design for testability (DFT) principles that enhance their ability to test these networks when combined with the requisite analog test plans. >

Proceedings ArticleDOI
29 Aug 1989
TL;DR: It is shown how the test-detect principle can be adapted to the parallel-patterns technique for combinational fault simulation, and the dominant-test-detECT approach has proved to be effective both for small sets of patterns, as might be used in automatic test pattern generation, and for larger pattern sets that might been used in built-in self-test.
Abstract: It is shown how the test-detect principle can be adapted to the parallel-patterns technique for combinational fault simulation. Several techniques for implementing a parallel-test-detect simulator are presented, with techniques based on nominator analysis providing the fastest fault simulation results. The dominant-test-detect approach has proved to be effective both for small sets of patterns, as might be used in automatic test pattern generation, and for larger pattern sets that might be used in built-in self-test. >

Journal ArticleDOI
TL;DR: The results indicate that this composite test generation strategy that uses multiple guidance heuristics was evaluated not only provides better fault coverage but also reduces the average time taken to generate a test or determine that a given fault is undetectable.
Abstract: The results of an extensive study of five existing testability measures when used to aid heuristics for automatic test pattern generation algorithms are presented. Each measure was evaluated using over 60000 faults in circuits of varying size and complexity. The performance of these measures was rated using several different criteria. Based on these results the performance of a composite test generation strategy that uses multiple guidance heuristics was evaluated. The results indicate that this strategy not only provides better fault coverage but also reduces the average time taken to generate a test or determine that a given fault is undetectable. >