Showing papers on "Automatic test pattern generation published in 1990"

A partial scan method for sequential circuits with feedback

Abstract: A method of partial scan design is presented in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with the sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles and reducing the sequential depth. Tests for the resulting circuit are generated by a sequential logic test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequence produced by the test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequences produced by the test generator. 98% fault coverage is obtained for a 5000-gate circuit by scanning just 5% of the flip-flops. >

The Ballast methodology for structured partial scan design

Abstract: An efficient partial scan technique called Ballast (balanced structure scant test) is presented. Scan path storage elements (SPSEs) are selected such that the remainder of the circuit has certain desirable testability properties. A complete test set is obtained using combinatorial automatic test pattern generation (ATPG). Some SPSEs may need to be provided with a HOLD mode; their number is minimized by ordering the registers in the scan path and formatting the test patterns appropriately. This methodology leads to a low area overhead and allows 100% coverage of irredundant faults. >

An optimization based approach to the partial scan design problem

Abstract: The problem of selecting flip-flops for inclusion into a partial scan path is formulated as an optimization problem. Scan flip-flops result in layout and delay overheads. Hence, scan flip-flops have to be chosen such that the net cost associated with these overheads is bounded by some user-specified limit. The problem then reduces to choosing a set of flip-flops which gives the best improvement in testability, while keeping the cost bounded. Cost functions are proposed for a standard cell design approach to model the effects of the overheads. Profit functions for three different testability criteria are proposed, and the optimization methodology for each is discussed. The optimization process is modeled on the lines of the 0/1 knapsack problem. Results for some medium-sized sequential circuits which show a very large improvement in fault coverage obtained by optimally selecting a small fraction of the flip-flops in the circuit are presented. >

Multiple distributions for biased random test patterns

Abstract: The test of integrated circuits by random patterns is very attractive, since no expensive test pattern generation is necessary and tests can be applied with a self-test technique or externally using linear feedback shift registers. Unfortunately, not all circuits are random-testable, because either the fault coverage is too low or the required test length too large. In many cases the random test lengths can be reduced by orders of magnitude using weighted random patterns. However, there are also some circuits for which no single optimal set of weights exists. A set of weights defines a distribution of the random patterns. It is shown that the problem can be solved using several distributions instead of a single one, and an efficient procedure for computing the optimized input probabilities is presented. If a sufficient number of distributions is applied, then all combinational circuits can be tested randomly with moderate test lengths. The patterns can be produced by an external chip, and an optimized test schedule for circuits with a scan path can be obtained. Formulas are derived to determine strong bounds on the probability of detecting all faults. >

Test generation for current testing (CMOS ICs)

Abstract: Current testing is useful for testing CMOS ICs because it can detect a large class of manufacturing defects, including defects that traditional stuck-at fault testing misses. The effectiveness of current testing can be enhanced if built-in current sensors are applied on-chip to monitor defect-related abnormal currents in the power supply buses. Such sensors have proved effective for built-in self-test. However, current testing requires the use of a special method to generate test vectors. The authors describe this method, which differs from that for traditional voltage-oriented testing, and postulate a test-generation algorithm for both on-chip and off-chip current testing. The algorithm uses realistic fault models extracted directly from the circuit layout. >

ATPG aspects of FSM verification

Abstract: Algorithms are presented for finite state machine (FSM) verification and image computation which improve on the results of O. Coudert et al (1989), giving 1-4 orders of magnitude speedup. Novel features include primary input splitting-this PODEM feature enlarges the search space but shortens the search due to implications. Another new feature, identical subtree recombination, is shown to be effective for iterative networks (eg, serial multipliers). The free-variable recognition feature prevents unbalanced bipartitioning trees in tautological subspaces. Finally, reached set pruning is significant when the image contains large numbers of previously reached states. >

An analytical approach to the partial scan problem

Abstract: The scan design is the most widely used technique used to ensure the testability of sequential circuits. In this article it is shown that testability is still guaranteed, even if only a small part of the flipflops is integrated into a scan path. An algorithm is presented for selecting a minimal number of flipflops, which must be directly accessible. The direct accessibility ensures that, for each fault, the necessary test sequence is bounded linearly in the circuit size. Since the underlying problem is NP-complete, efficient heuristics are implemented to compute suboptimal solutions. Moreover, a new algorithm is presented to map a sequential circuit into a minimal combinational one, such that test pattern generation for both circuit representations is equivalent and the fast combinational ATPG methods can be applied. For all benchmark circuits investigated, this approach results in a significant reduction of the hardware overhead, and additionally a complete fault coverage is still obtained. Amazingly the overall test application time decreases in comparison with a complete scan path, since the width of the shifted patterns is shorter, and the number of patterns increase only to a small extent.

Testing for parametric faults in static CMOS circuits

Abstract: The authors compare the cost of testing for excess of I/sub DDQ/ caused by bridge, break, and transistor stuck-on faults versus the cost of traditional testing methods. It is shown that, since many defects, cause nonlogical faults, I/sub DDQ/ monitoring during the application of test vectors to an IC provides significantly higher defect coverage than using only conventional testing. The costs for I/sub DDQ/ testing are compared with those for SSF (single-stuck-at-fault) testing by modifying an existing SSF ATPG (automatic test pattern generation) system. It is concluded that test generation for I/sub DDQ/ faults is quicker and more complete than for equivalent SSF faults, and even without explicit I/sub DDQ/ test generation, I/sub DDQ/ monitoring can be added to existing SSF testing for increased defect coverage. >

A diagnostic test pattern generation algorithm

Abstract: The authors present a novel ATPG (automatic test pattern generation) algorithm, based on PODEM, that makes diagnostic test pattern generation feasible for medium-sized combinational circuits described at the gate level with the single-stuck-at-fault assumption. The input to the ATPG is a couple of faults, and either the output is a test pattern that distinguishes them or they are tagged as indistinguishable. The need to consider the fault-free circuit and the two faulty circuits at the same time required the extension of the algebra to encompass two additional values, Delta and delta . A Delta appears on the nodes of the circuit whenever a difference between the two faulty circuits exists. The presence of a delta marks the locations where a difference might exist if the X values on one or both faulty circuits were suitably set. The algorithm excites and propagates Delta s onto the primary outputs and is thus called the Delta -algorithm. Preliminary results on a set of benchmark circuits are reported. >

A statistical theory of digital circuit testability

Abstract: A relation between the average fault coverage and circuit testability is developed. The statistical formulation allows computation of coverage for deterministic and random vectors. The following applications of this analysis are discussed: determination of circuit testability from fault simulation, coverage prediction from testability analysis, prediction of test length, and test generation by fault sampling. >

Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets.

Abstract: Simplified ATPG and fault simulation algorithms, reduced test set sizes, and increased fault coverage are achieved with I, testing for stuck-at faults. In addition, IDm testing will detect logically redundant and multiple stuck-at faults and improve the detection of non-stuck-at fault defects.

Optimal test set design for analog circuits

Abstract: Given the high cost of testing analog circuit functionality, it is proposed that tests for analog circuits should be designed to detect faults. An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault. Examples demonstrate that drastic reductions in test time can be achieved without sacrificing fault coverage. >

ATPG for ultra-large structured designs

Abstract: A ATPG (automatic test pattern generation) system that can efficiently create a high-coverage test for extremely large scan designs is described This system is formed by optimally combining a fast fault simulator with a powerful test generator For the ISCAS85 and ISCAS89 circuits, this ATPG system created a test for all testable faults and identified all redundant faults without a single aborted fault This represents the first time this has been achieved for the ISCAS89 designs, and the performance of this ATPG system is significantly better than published results Performing ATPG for the largest ISCAS89 designs, which contained about 25000 gates, required only 3 min of CPU time on an Apollo DN3550 workstation The data collected for the ISCAS designs showed that the ATPG CPU time increased linearly with gate count This strongly suggests that ATPG can be efficiently performed for circuits of 100000 and even one million gates >

A method to calculate necessary assignments in algorithmic test pattern generation

Abstract: The authors present a novel test pattern generation algorithm which uses the concept of necessary assignments to reduce or eliminate backtracking in automatic test pattern generation. Necessary assignments are those which must be made in order to find a test pattern; without them the search is guaranteed to fail. The algorithm is based on the mathematical concept of images and inverse images of set functions. In order to take advantage of formal concepts developed for Boolean algebras, the algorithm uses a 16-valued algebra. It has been used to generate test patterns for all faults in a variety of benchmark circuits. Experimental results indicate that the algorithm is particularly efficient at redundancy identification, which is often a problem for conventional test pattern generation algorithms. The benefits of a 16-valued system are illustrated through examples of faults which are not properly handled by conventional 5- or 9-valued systems. >

Functional test generation for finite state machines

Abstract: A functional test generation method for finite-state machines is described. A functional fault model, called the single-transition fault model, on the state transition level is used. In this model, a fault causes a single transition to a wrong destination state. A fault-collapsing technique for this fault model is also described. For each state transition, a small subset of states is selected as the faulty destination states so that the number of modeled faults for test generation is minimized. On the basis of this fault model, the authors developed an automatic test generation algorithm and built a test generation system. The effectiveness of this method is shown by experimental results on a set of benchmark finite-state machines. A 100% stuck-at fault coverage is achieved by the proposed method for several machines, and a very high coverage (>97%) is also obtained for other machines. In comparison with a gate-level test generator STG3, the test generation time is speeded up by a factor of 100. >

Built-in self-testing of random-access memories

Abstract: Built-in self-test (BIST) methods are examined, including the fault models and the test algorithms on which the BIST implementations are based. The notion of generic test architectures suitable for implementing a wide variety of test algorithms is introduced. A taxonomy for test architectures is provided and used to categorize BIST implementations, and important implementations are surveyed. It is demonstrated that BIST is a viable solution to the problem of testing large memories and that approaches based on test architectures rather than on test algorithms are more versatile and will likely predominate in the future. >

Behavioral fault simulation in VHDL

Abstract: Two tools which facilitate a fault simulation of behavioral models described using the VHSIC hardware description language (VHDL) are presented. The first tool is the behavioral fault mapper (BFM). The BFM algorithm accepts a fault-free VHDL model and a fault-list of N faults from which it produces N faulty models. The process of mapping the faults in the fault-list onto copies of the original VHDL model is automated. The N faulty models are immediately suitable for fault simulation. The second tool presented is test bench generator (TBG). The TBG algorithm creates the VHDL testbench and all other files necessary to complete a batch-mode fault simulation of the N faulty models. >

Diagnosis oriented test pattern generation

Abstract: This paper addresses the generation of test patterns having diagnostic properties. The authors goal is to produce patterns able not only to detect, but also to distinguish faults in combinational circuits. A general formalization of the problem is first given; a new technique is then introduced to improve the diagnostic capabilities of a traditional automatic test pattern generation (ATPG); the experimental results showing its effectiveness are finally presented. >

EST: the new frontier in automatic test-pattern generation

Abstract: An algorithm, called EST, is presented which is a new combinatorial automatic test-pattern generation (ATPG) branch-and-bound search algorithm, based on the generation of equivalent logic decompositions (search states) at each search decision point. The E-frontier is an efficient representation of a search state and is used with a hashing algorithm to detect equivalent search states. When EST matches an equivalent search state from a prior fault, and both prior and current faults are sensitized, EST completes the current fault test-pattern with values from the prior fault test-pattern and terminates search immediately. A new method of redundant fault analysis is also introduced that uniquely determines signal values for subsequent test-pattern search. Results show that this algorithm accelerates the base ATPG algorithm by a factor of 1.03 to 328 when considering all faults, a factor of 1347:1 for hard-to-test faults and a factor of 200000 for certain redundancy proofs for the test cases shown. >

Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test sets

Abstract: The authors discuss the significant improvements that were achieved when a conventional ATPG (automatic test pattern generation) algorithm was modified to generate test sets suitable for I/sub DDQ/ testing. These improvements include increased SAF (stuck-at-fault) coverage, reduced vector set sizes, coverage of logically redundant SAFs and multiple SAFs, increased coverage of CMOS IC non-SAF defects, and reduced CPU cost for ATPG and fault simulation. This reduction in computational complexity for I/sub DDQ /based ATPG enables test generation for much larger circuits than previously possible. Additionally untestable faults can be further categorized to identify SAFs that are truly 'don't-care faults,' thereby offering a more realistic assessment of actual fault coverage. >

Toward massively parallel automatic test generation

Abstract: A new automatic test pattern generation (ATPG) methodology that has the potential to exploit fine-grain parallel computing and relaxation techniques is described. This approach is radically different from the conventional methods used to generate tests for circuits from their gate level description. The digital circuit is represented as a bidirectional network of neurons. The circuit function is coded in the firing thresholds of neurons and the weights of interconnection links. This neural network is suitably reconfigured for solving the ATPG problem. A fault is injected into the neural network and an energy function is constructed with global minima at test vectors. The authors simulated the neural network on a serial computer, and determined the global minima of the energy function using a directed search technique augmented by probabilistic relaxation. Preliminary results on combinational circuits confirm the feasibility of this technique. >

Partial scan by use of empirical testability

Abstract: The objective of the partial scan method proposed is to obtain maximum fault coverage for the number of scan elements selected. Empirical testability difference (ETD), a measure of the potential improvement in the overall testability of the circuit, is used to successively select storage elements for scan. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the actual test sequence generator. In addition, ETD focuses on the hard-to-detect faults rather than all faults once such faults are known. The method has been extensively tested with ten of the sequential circuits given by F. Brglez et al. (1989) using the FASTEST provided by T. Kelsey and K. Saluja (1989). The results of these tests indicate that ETD yields on average either 27% of the number of uncovered faults for the same number of scan elements or 21% fewer scan elements for the same fault coverage compared to the other methods studied. >

Why is less information from logic simulation more useful in fault simulation

Abstract: The authors propose a novel linear-time algorithm for identifying, in a large combinatorial circuit, a large set of faults that are undetectable by a given test vector. Although this so-called X-algorithm does not identify all the undetectable faults, empirical evidence is offered to show that the reduction in the number of remaining faults to be simulated is significant. The algorithm is intended as a simple, fast preprocessing step to be performed after a test vector has been generated, but before the (often lengthy) process of fault simulation begins. The empirical results indicate that the X-algorithm is both useful (indicated by the utility factor) and good (indicated by the effectiveness factor). It provides as much as a 50% reduction in the number of faults that need to be simulated. Moreover, the algorithm seems to identify a large fraction of the undetectable faults. >

Efficient generation of test patterns using Boolean satisfiability

Abstract: A combinational circuit can be tested for the presence of a single stuck-at fault by applying a set of inputs that excite a verifiable output response in that circuit. If the fault is present, the output will be different than it would be if the fault were not present. Given a circuit, the goal of an automatic test pattern generating system is to generate a set of input sets that will detect every possible single stuck-at fault in the circuit. This dissertation describes a new method for generating test patterns: the Boolean satisfiability method. The new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits. Second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from most programs now in use, which directly search the circuit data structure instead of constructing a formula from it. The new method is quite general and allows for the addition of any heuristic used by the structural search methods. The Boolean satisfiability method has produced excellent results on popular test pattern generation benchmarks.

A single-state-transition fault model for sequential machines

Abstract: A fault model in the state transition level of finite state machines is studied. In this model, called a single-state-transition (SST) fault model, a fault causes a state transition to go to a wrong destination state while leaving its input/output label intact. An analysis is given to show that a test set that detects all SST faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. It is shown that, for an N-state M-transaction machine, the length of the SST fault test set is upper-bounded by 2*M*N/sup 2/ while the length is exponential in terms of N for a checking experiment. Experimental results show that the test set generated for SST faults achieves not only a high single stuck-at fault coverage but also a high transistor fault coverage for a multilevel implementation of the machine. >

Interconnect testing of boards with partial boundary scan

Abstract: It is shown that interconnect testing for boards that mix boundary scan and conventional components can be performed effectively by a four-stage strategy: a conventional shorts test where the tester has access, a scan circuitry integrity test, a fairly conventional boundary scan interconnect test, and a test for shorts between the boundary scan and conventional parts of the circuit, which is new. There are a number of complications so that careful analysis of the results is needed, even for the conventional parts of the test, but this strategy can be used to give a precise, usable diagnosis of the problems. It is noted that a circuit is not necessarily testable just because it contains boundary scan parts. The test access port on those components is a potential weak link, and physical access to those signals is necessary to get good diagnosis. In addition, it may be impossible to diagnose accurately shorts involving nodes with neither physical access nor boundary scan access, and that may even repeatedly not be detectable. >

High level test generation using data flow descriptions

Abstract: To significantly expedite the test generation process for sequential VLSI circuits, the hierarchy in the circuit descriptions should be exploited. Conventional test generators can provide tests for relatively small modules, which are typically embedded in large circuits. This paper considers test generation for complex VLSI circuits composed of many interconnected modules. In contrast to the previous approaches, the authors use high-level primitives and data flow descriptions to perform hierarchical test generation. Data flow descriptions provide the set of valid control signals to be activated for a particular data path to be active. Sequential propagation and justification of signals is carried out recursively. Results are presented based on an implementation of the algorithm in LISP on a Texas Instruments Explorer. >

Speed up of test generation using high-level primitives

Abstract: A general methodology to speed up the test generation process for combinational circuits with high-level primitives is proposed. The technique is able to handle circuits in a hierarchical fashion, treats the signal at a bit-vector level rather than the bit level and takes advantage of the complex operations that are available in the computer system. The technique has been implemented and the results are presented for five circuits. It is shown that by using the high-level primitives a significant speed-up and significant reduction in storage requirement are achieved. More importantly, the reduction in storage size permits test generation for very large circuits. It is clear that use of high-level primitives is more efficient than use of low-level primitives in test generation. A dependency-directed backtracking mechanism is also present which reduces the number of backtracks. The technique presented is complete, permits test vector generation for a broad class of large circuits with complex primitives, and accommodates a very general fault model. >

Finite state machine synthesis with embedded test function

Abstract: We propose a synthesis for a testability method in which the test function is incorporated into the state diagram of the finite state machine (FSM). The test function is specified as an FSM with the same number of state variables as the given object machine. Based upon the chosen test methodology, a variety of test functions can be defined. As an illustration, we construct a test machine in which each state is uniquely set and observed by an input sequence no longer than ⌈log k n⌉, wheren is the number of states and the integerk is a design parameter. The state transition graph of the test machine is superimposed on the state graph of the object function such that a minimal number of new transitions are added. State assignment, logic minimization, and technology mapping are carried out for the combined graph. By design, the embedded test machine is fully testable. Also, since the test machine can control all memory elements, the circuit is effectively tested by a combinational circuit test generator. Scan register is shown to be a special case in this methodology.

Generating pseudo-exhaustive vectors for external testing

Abstract: Over the past years special chips for external tests have been successfully used for random pattern testing The authors present a technique for combining the advantages of such a low-cost test with the advantages of pseudoexhaustive testing, which are enhanced fault coverage and simplified test pattern generation To achieve this goal, two tasks are accomplished First, an algorithm is developed for pseudoexhaustive test pattern generation, which ensures a feasible test length Second, a chip design for applying these test patterns to a device under test is presented The chip is programmed by the output of the proposed algorithm and controls the entire test The technique is first applied to devices with a scan path and then extended to sequential circuits A large number of benchmark circuits have been investigated, and the results are presented >