Showing papers on "Automatic test pattern generation published in 1992"

CRIS: a test cultivation program for sequential VLSI circuits

Abstract: This paper discusses a novel approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The approach uses hierarchical simulation technique in the analysis to drastically reduce the memory requirement, thus allowing the test generation for large VLSI circuits. The algorithms are at the switch level so that general MOS digital designs can be handed, and both stuck-at and transistor faults are handle accurately. The approach has been implemented in a hierarchical test generation system, CRIS, that runs under UNM on SPARC workstations. CRIS has been used successfully to generate tests with high fault coverage for large combinational and sequential circuits.

The power test for data dependence

Abstract: A data dependence decision algorithm called the power test is introduced. The power test is a combination of the extended GCD algorithm and the Fourier-Motzkin method to eliminate variables in a system of inequalities. This is the first test that can generate the information needed for some advanced transformations, and that can handle complex simultaneous loop limits. Previous work in data dependence decision algorithms is reviewed. Some examples which motivated the development of this test are examined, including those which demonstrate the additional power of the power test. Although it may be too expensive for use as a general-purpose dependence test in a compiler, the power test has proved useful in an interactive program restructuring environment. >

Delay fault models and test generation for random logic sequential circuits

Abstract: The authors study the problem of delay fault modeling and test generation for any random logic sequential circuit. The proposed test generation method, based on transition and hazard states of signals, is applicable to any sequential circuit of either non-scan, scan or scan-hold type of design. Three fault models based on different initial state assumptions during the propagation of the fault effect to a primary output are proposed and analyzed using the proposed delay fault test generation method. A novel thirteen-value algebra is considered to simplify the analysis of robust and nonrobust tests during fault simulation of path delay faults. >

Skewed-Load Transition Test: Part II, Coverage

Abstract: A skewed-load transition test is a delay test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. This paper concentrates on the issue of coverage in skewed-load transition test. A topological lower bound of the transition test coverage is derived. This bound is shown to work well for the entire family if ISCAS combinational circuits. It is also shown that input ordering plays a key role in the attainable transition fault coverage. The paper describes a heuristic for input ordering that will achieve a nearly optimal transition fault coverage.

Test generation by environment emulation

Abstract: Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit. A fault dictionary is produced which includes an indication of the test vector at which each fault is detected, the output signal differences indicative of fault detection, and a log of the faults detected. The faultable emulation is also used for device testing by comparing its outputs to those of a logic circuit, and injecting selected faults (for example, those indicated by comparing failure patterns to fault dictionary entries) to aid in device debug. Techniques are described for modeling faults, sequentially activating the faults in hardware time, preparing a fault dictionary, and extracting a test program in a format adaptable to standard ATE systems, and testing a debugging devices by comparing their behavior to that of a faultable emulation model of the device.

The multiple observation time test strategy

Abstract: The authors consider the test generation problem, for synchronous sequential circuits in the case where hardware reset is not available (or cannot be assumed to be fault free). It is shown that the conventional testing approach, in which a fault is detected at a single predetermined time unit along the test sequence and in which the response of the circuit under test is compared against a single fault-free response, valid for all initial states of the circuit, can cause detectable faults to be declared undetectable. The use of a small number of different observation times and a small number of fault-free responses can allow the fault to be detected. Based on this observation, the use of multiple fault free responses and multiple time units for observation of the response of the circuit under test is suggested and test generation algorithms under the multiple observation time test strategy are given. Experimental results demonstrate the effectiveness and practicality of the multiple-observation-time strategy in increasing the fault coverage. >

Diagnostic Fault Simulation of Sequential Circuits

Abstract: In this work we describe a diagnostic fault simulator for sequential circuits which evaluates the effectiveness of a given test set in distinguishing between faults. Diagnostic fault simulation is performed on several ISCAS89 sequential benchmark circuits using two diferent deterministic test sets for each circuit. Several diagnostic measures are reported, including the diagnostic resolution, the diagnostic power, and the sizes of the indistinguishable fault classes. In addition, lists of indistinguishable faults are generated. Use of the diagnostic fault simulator to diagnose faults, given the output responses of failing devices, is also described.

Circuit design for built-in current testing

Abstract: In current testing, the number of test vectors is usually A testing circuit for built-in current testing is proposed and a test generation method using the testing circuit is described. The function of the testing circuit is to measure the integral of the current including the dynamic current during a certain time interval and to judge whether the Cuir is fault-free or not by the measured value. The function01 speed of the testing circuit is rapid because this measuring method is not influenced by any dy,rlamic current. We also describe the test generation method briefly. The test sequences cause almost equal dymmic current between every two test vectors. The number of test vectors in each test sequence is less than that of the traditional testing for stuck-at faults.

ROTCO: a reverse order test compaction technique

Abstract: In this paper, the authors consider the problem of reducing the test set sizes for single stuck-at faults in combinational logic circuits. They report on an alternative to the conventional reverse order fault simulation, called reverse order test compaction (ROTCO). The proposed procedure processes a test set obtained by an existing test generator, with the sim of reducing the test set size. Unlike reverse order fault simulation, the proposed procedure allows the test vectors to be changed in order to increase the flexibility in detecting faults detected by earlier vectors, thereby potentially removing tests that cannot be removed by reverse order fault simulation. Experimental results for ISCAS-85 and PLA benchmark circuits are presented to demonstrate the effectiveness of the proposed procedure. >

Test compaction for sequential circuits

Abstract: The authors describe a number of heuristic algorithms to compact a set of test sequences generated by a sequential circuit automatic test pattern generator (ATPG). A model has been developed and analyzed which shows that finding the optimal solution has an exponential worst-case complexity. To achieve an acceptable run time, some heuristics have been developed that yield good suboptimal solutions in a very short time. Three heuristic algorithms were developed. These algorithms were implemented in C and lex and applied to several of the ISCAS-89 benchmark sequential circuits. They reduce the test length by 17%-63% with a very small time overhead, while having little effect on the original fault overage. >

A design for testability scheme to reduce test application time in full scan

Abstract: Full scan is a widely accepted design for testability technique for sequential circuits. However, the test application time required by full scan could be high because of the necessity to scan in and scan out test vectors. In this paper, a hybrid scheme is presented that aims to reduce test application time in circuits with full scan. The proposed scheme exploits the inherent sequential nature of the circuit in conjunction with the additional controllability and observability available through full scan. Also, it is shown that the hybrid scheme has an additional advantage of being suited for testing transition faults. >

The pseudoexhaustive test of sequential circuits

Abstract: The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the test strategy requires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the well-known benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation. >

A small test generator for large designs

Abstract: We report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. the fraction of faults that are resolved, are comparable to or better than those reported previously in the literature. No preprocessing is required and the amount of memory needed is less than 100 bytes per gate. The low memory requirements and high performance have been achieved by working with a larger but simpler search space, by simplifying decision making and backtracking and by using only implication techniques that are fast and that require no preprocessing.

A functional fault model for sequential machines

Abstract: A fault model at the state transition level is proposed for finite state machines. In this model, a fault causes the destination state of a state transition to be faulty. Analysis shows that a test set that detects all single-state-transition (SST) faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2MN/sup 2/ for an N-state M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine. >

A novel approach to delay-fault diagnosis

Abstract: The authors discuss possibilities of delay fault diagnosis based on fault simulation. They detail the proposed approach based on critical path tracing. A path tracing process is presented with information provided by a logic simulation. Due to the limitations induced by such a simulation, a reliable approach is described based on a six-valued logic simulation. It requires no delay size based fault models and considers only the fault-free circuit. This method is an alternative to fault simulation based approaches and provides perfectly reliable results. It does not require timing evaluations and can be very accurate. >

Equivalence of robust delay-fault and single stuck-fault test generation

Abstract: A link between the problems of robust delay-fault and single stuck-fault test generation is established. In particular, it is proved that all the robust test vector pairs for any path delay-fault in a network are directly obtained by all the test vectors for a corresponding single stuck-fault in a modified network. Since single stuck-fault test generation is a well solved problem, this result yields an efficient algorithm for robust delay-fault test generation. Experimental results demonstrate the efficiency of the proposed technique. >

At-speed delay testing of synchronous sequential circuits

Abstract: Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length. >

Diagnosis of leakage faults with I DDQ

Abstract: Recently there has been renewed interest in fault detection in static CMOS circuits through I DDQ monitoring. This work shows that, in addition to fault detection, accurate fault diagnosis may be performed using a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis, and as a result requires only minor modifications to existing stuck-at fault ATPG software. The associated hardware is sufficiently simple that on-board implementation is possible. Experimental results demonstrate the effectiveness of the method on a standard-cell ASIC.

An efficient non-enumerative method to estimate path delay fault coverage

Abstract: A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths.

Exact evaluation of diagnostic test resolution

Abstract: The authors introduce a new measure of the diagnostic resolution of a test set: the sizes of all equivalence classes in the circuit under the test set. This measure is a better indicator of the diagnostic capabilities of a test set than single-value metrics based on undistinguished pairs of faults or completely distinguished faults. A symbolic algorithm for computing equivalence class sizes has been used to evaluate the diagnostic resolution of deterministic single-stuck-at fault test sets for ISCAS combinational and sequential benchmark circuits. >

Method for automatically generating test vectors for digital integrated circuits

Abstract: A sequential circuit test generation system and method to generate test patterns for sequential without assuming the use of scan techniques or a reset state utilizes the iterative logic array (ILA) model of the sequential circuit and a targeted-D propagation scheme employing both forward time processing (FTP) and reverse time processing (RTP) techniques for assigning a sequence of primary input (PI) values and for producing a an initial pseudo primary input (PPI) vector representing the initial state of the digital circuit at a particular time frame Improved state justification techniques generate the remaining sequence of PI vectors necessary to put the circuit into the initial state from either known or don't care first states, by means of a heuristic method for reducing required initial state assignments The method can also be applied to reduce the required number of PI vector assignments is also presented In another phase of test vector generation, knowledge about the digital circuit behavior is obtained from a fault simulator to identify circuit nodes at which error signals are activated and partly propagated by already generated sequences of test vectors, and this knowledge is utilized with FTP techniques to generate test vector sequences for these nodes

Advanced fault collapsing (logic circuits testing)

Abstract: The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well. >

An algorithm to reduce test application time in full scan designs

Abstract: Full scan design technique alleviates the test gen- eration problem for sequential circuits. However scan operations increase the number of test clocks substan- tially. This paper presents an algorithm to generate a test with fewer test clocks for full scan designs by us- ing combinational and sequential test generation algo- rithms adaptively. Heuristics combining test measures and scan strategies are introduced. The algorithm, Test Application time Reduction for Full scan deszgns (TARF), is implemented and tested on a set of ISCAS sequential benchmark circuits. The results show that TARF achieves same test coverage as combinational test generators but with fewer test clocks.

Parallel-processing techniques for automatic test pattern generation

Abstract: Some of the more widely used serial automatic test pattern generation (ATPG) algorithms and their stability for implementation on a parallel machine are discussed. The basic classes of parallel machines are examined to determine what characteristics they require of an algorithm if they are to implement it efficiently. Several techniques that have been used to parallelize ATPG are presented. They fall into five major categories: fault partitioning, heuristic parallelization, search-space partitioning, functional (algorithmic) partitioning, and topological partitioning. In each category, an overview is given of the technique, its advantages and disadvantages, the type of parallel machine it has been implemented on, and the results. >

An efficient delay test generation system for combinational logic circuits

Abstract: An efficient delay test generation (DTEST GEN) system for combinational logic circuits is presented. In the DTEST GEN system, delay testing problems are divided into gross delay faults and small delay faults separately so that the tradeoff between the levels of delay testing effort and the confidence levels of proper system operation can be explored. Complete automatic test pattern generation (ATPG) algorithms are proposed for both gross delay faults and small delay faults. A novel timing analysis method for delay test generation which uses a conventional depth-first search technique and a novel functionality analysis technique is introduced. The functionality analysis technique examines, necessary conditions for a given delay fault to be testable and estimates the upper bound of the good circuit propagation delay of the longest sensitizable path passing through the fault site. Several benchmark results are demonstrated for both gross delay fault testing and small delay fault testing. >

Estimating testing effectiveness of the circular self-test path technique

Abstract: The effectiveness of a random built-in self-test technique for VLSI circuits is studied. This technique, called the circular self-test path (CSTP), is applicable to circuits that consist of combinational blocks and registers. In particular, the effectiveness of test pattern generation, the effectiveness of test response compaction and fault coverage are examined. The test generation effectiveness is evaluated by the fraction of all possible test patterns applied during a testing session to the circuit under test. The compaction effectiveness of the CSTP technique is measured by the probability of aliasing, and fault coverage by the fraction of all permanent faults that are detected. For all these measures, simple formulas are developed, which give very accurate estimations without detailed circuit simulation. To demonstrate their accuracy, the estimates obtained by the formulas are compared to the results obtained by extensive simulation experiments. >

Delay-fault diagnosis by critical-path tracing

Abstract: A delay fault diagnosis process consisting of simulation of the fault-free circuit with a four-valued logic algebra and critical-path tracing from primary outputs to primary inputs is presented. An alternative to fault simulation, the method requires no delay-size-based fault models and considers only the fault-free circuit. A sensitivity analysis process for improving diagnosis accuracy is also presented. >

The revealing power of a test case

Abstract: ‘Propagation, infection, and execution analysis’ (termed PIE) is used for predicting where faults can more easily hide in software. To make such predictions, programs are dynamically executed with test cases, and information concerning the test cases is collected into a histogram, each bin of which represents a single test case. The score in a bin predicts the likelihood that the test case will reveal a fault through the production of a failure (if a fault exists in the set of program locations that the test case executes). Preliminary experiments using program mutations suggest that the histogram technique presented in this paper can rank test cases according to their fault revealing ability.

Delay fault test generation for scan/hold circuits using Boolean expressions

Abstract: A new test generation technique for path delay faults in scan/hold type circuits is presented. It uses reduced ordered binary decision diagrams to represent Boolean functions implemented by the subcircuits in a circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit under test and a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated for each fault. These constraints are then manipulated to obtain robust tests, if they exist; otherwise, nonrobust tests are obtained from the constraint functions, if they exist. An implementation of this technique was used to analyze delay fault testability of several ISCAS '89 benchmark circuits. >